Implicit DMA Question

[theklap]

Thanks for the test ROM, it has helped me with some timing issues.

Under TEST_ImplicitDMAAbort

I can pass the test with - "; success code 2. (pre-1990 CPU)"

When trying to add the logic to pass with - "; success code 1. (post-1990 CPU)", I am failing test 4

What is TEST_ImplicitDMAAbort_AltKey3 measuring and returning?
TEST_ImplicitDMAAbort_AltKey3:
.byte $01, $01, $01, $04, $04, $04, $04, $04, $04, $04, $04, $04, $04, $04, $04, $04

My TEST_ImplicitDMAAbort_AltKey1 and TEST_ImplicitDMAAbort_AltKey2 match the expected result, just not TEST_ImplicitDMAAbort_AltKey3.
My result is matching TEST_ImplicitDMAAbort_Key3 instead of the ALT behavior.

Just FYI: I am passing all other PPU, APU tests, I am failing some unofficial CPU opcode stuff, mainly Unofficial Instructions: SHA, SHX, SHY and then under Unofficial Instructions starting at test K fail.

[100thCoin]

The third test here is pretty much running the same test as error code 1 and 2, but while keeping the DMC looping behavior active. This means the implicit abort behavior will not occur for the test used in error code 3.

This test measures how long (in CPU cycles) a routine took. I need to do more research into the DMA myself, because I'm not sure why the post-1990 CPUs behave differently.

Comparing the "answer keys" from the pre/post-1990 CPUs, the post-1990 CPUs seem to have a 4 cycle DMA occur when the write to $4015 happens 1 and 2 cycles before the instance where a 1-cycle DMA occurs. I'm unsure what the cause is, it but looks like the same behavior is present in test 3, where there are 2 instances where the pre-1990 CPU would take 1 cycle, and the post-1990 CPU would run a DMA.

I'll try and write some clearer comments for this test, though to be honest I don't fully understand this behavior myself. I just recorded the values I got when running this test on some consoles.

[theklap]

Thanks for that, I think I figured it out timing-wise.

Enable DMC write to 4015 (with an empty sample buffer, looping enabled, and bytes remaining = 1), 3 APU cycles (6 or 7 CPU cycles) before reload will cause a 4 cycle implict DMA.

At least that's the logic I used to pass the test.....