Clock skew modeling from SDF clock path delays

[robtaylor]

Summary

Model per-DFF clock arrival times from SDF INTERCONNECT delays on clock paths, rather than assuming an ideal single clock edge.

Current State

GEM assumes all DFFs receive the clock at time 0. In reality, CTS (clock tree synthesis) inserts buffers with varying delays, so each DFF sees a different clock arrival time. These delays are present in the SDF but currently ignored for clock paths.

Proposed Approach

• Identify clock network paths in SDF (INTERCONNECT entries leading to DFF clock pins)
• Compute per-DFF clock arrival offset
• Adjust setup/hold checks: setup_slack = (clock_arrival + clock_period) - data_arrival - setup_time
• Expose per-DFF clock skew in timing reports

Impact

High — CTS delays are real and can be hundreds of picoseconds. Ignoring them makes setup/hold checks unreliable.

Effort

Medium — need to trace clock paths through SDF and modify the constraint checking logic.