Possible FPGA optimization: Reduce TDMA bits to 24 #71
Description
The communication between the FPGA runs a 5xTDMA8 @32bits in both directions (40 channels each). However out of these 32bits only 24 are used.
(The situation between DSP1 and DSP2 is different as we currently send 32bit floats up and down).
I am a very beginner to VHDL and I haven't had time to study the FPGA code, BUT: Perhaps we can reduce the utlization of the FPGA by reducing the bit depth from 32 to 24?
From reading the reference manual it seems to me that the DSP supports 24bit TDMA's. Also the clock is being divided so we can just divide by 3 instead of 4 to achieve the same framerate?
Disadvantage: It wouldn't be possible to send floats to a second X32 over AES50 if we chose to connect two X32's into one virtual mixing console.
It seems to me that we need to optimize everything in the FPGA as we are running out of space (if we would use both AES50 ports) and there are still more features which we might want to implement in the future (such as more channels through TDMA16 od TDMA24 towards the DSP1)