From cb66c49730ffeb6bf49ebd552e54bbf2a2818730 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Mon, 30 Mar 2026 19:30:08 +0200 Subject: [PATCH] add vhdl frontend support via ghdl I added the ghdl frontend to also support vhdl files. I also added a "counter" example for sky130hd and ihp-sg13g2 with VHDL code. Signed-off-by: Friedrich Beckmann --- flow/Makefile | 2 ++ flow/designs/ihp-sg13g2/counter/config.mk | 21 +++++++++++++++++++ .../designs/ihp-sg13g2/counter/constraint.sdc | 15 +++++++++++++ flow/designs/sky130hd/counter/config.mk | 16 ++++++++++++++ flow/designs/sky130hd/counter/constraint.sdc | 15 +++++++++++++ flow/designs/src/counter/counter.vhd | 19 +++++++++++++++++ flow/scripts/synth_preamble.tcl | 9 +++++++- flow/scripts/variables.yaml | 9 +++++++- 8 files changed, 104 insertions(+), 2 deletions(-) create mode 100644 flow/designs/ihp-sg13g2/counter/config.mk create mode 100644 flow/designs/ihp-sg13g2/counter/constraint.sdc create mode 100644 flow/designs/sky130hd/counter/config.mk create mode 100644 flow/designs/sky130hd/counter/constraint.sdc create mode 100644 flow/designs/src/counter/counter.vhd diff --git a/flow/Makefile b/flow/Makefile index 7bccdc8307..8f03946610 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -44,6 +44,7 @@ # DESIGN_CONFIG=./designs/sky130hd/chameleon/config.mk # DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk # DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk +# DESIGN_CONFIG=./designs/sky130hd/counter/config.mk # DESIGN_CONFIG=./designs/sky130hd/jpeg/config.mk # DESIGN_CONFIG=./designs/sky130hd/microwatt/config.mk # DESIGN_CONFIG=./designs/sky130hd/riscv32i/config.mk @@ -77,6 +78,7 @@ # DESIGN_CONFIG=./designs/gf180/uart-blocks/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/aes/config.mk +#DESIGN_CONFIG=./designs/ihp-sg13g2/counter/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/ibex/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/gcd/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/spi/config.mk diff --git a/flow/designs/ihp-sg13g2/counter/config.mk b/flow/designs/ihp-sg13g2/counter/config.mk new file mode 100644 index 0000000000..9ed0c46a58 --- /dev/null +++ b/flow/designs/ihp-sg13g2/counter/config.mk @@ -0,0 +1,21 @@ +export DESIGN_NICKNAME = counter +export DESIGN_NAME = counter +export PLATFORM = ihp-sg13g2 + +export VHDL_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/counter/*.vhd)) + +export SYNTH_HDL_FRONTEND = ghdl + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 20 +export CORE_ASPECT_RATIO = 1 + +export PLACE_DENSITY = 0.65 +export TNS_END_PERCENT = 100 + +export USE_FILL = 1 + +export REMOVE_ABC_BUFFERS = 1 + + diff --git a/flow/designs/ihp-sg13g2/counter/constraint.sdc b/flow/designs/ihp-sg13g2/counter/constraint.sdc new file mode 100644 index 0000000000..57701f459d --- /dev/null +++ b/flow/designs/ihp-sg13g2/counter/constraint.sdc @@ -0,0 +1,15 @@ +current_design counter + +set clk_name core_clock +set clk_port_name clk +set clk_period 10.0 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/counter/config.mk b/flow/designs/sky130hd/counter/config.mk new file mode 100644 index 0000000000..401955dac5 --- /dev/null +++ b/flow/designs/sky130hd/counter/config.mk @@ -0,0 +1,16 @@ +export DESIGN_NICKNAME = counter +export DESIGN_NAME = counter +export PLATFORM = sky130hd + +export VHDL_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/counter/*.vhd)) + +export SYNTH_HDL_FRONTEND = ghdl + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.25 +export TNS_END_PERCENT = 100 + +export REMOVE_ABC_BUFFERS = 1 + diff --git a/flow/designs/sky130hd/counter/constraint.sdc b/flow/designs/sky130hd/counter/constraint.sdc new file mode 100644 index 0000000000..57701f459d --- /dev/null +++ b/flow/designs/sky130hd/counter/constraint.sdc @@ -0,0 +1,15 @@ +current_design counter + +set clk_name core_clock +set clk_port_name clk +set clk_period 10.0 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/src/counter/counter.vhd b/flow/designs/src/counter/counter.vhd new file mode 100644 index 0000000000..6503888626 --- /dev/null +++ b/flow/designs/src/counter/counter.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is + port( + en_i : in std_ulogic; + cnt_o : out unsigned(15 downto 0); + clk : in std_ulogic; + rst_n : in std_ulogic + ); +end counter; + +architecture rtl of counter is + signal cnt : unsigned(cnt_o'range); +begin + cnt <= (others => '0') when rst_n = '0' else cnt + 1 when en_i = '1' and rising_edge(clk); + cnt_o <= cnt; +end rtl; diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 3edee2d454..26974f9f33 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -103,10 +103,17 @@ proc read_design_sources { } { # Apply top-level parameters chparam -set $key $value $::env(DESIGN_NAME) } - if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { error "Non-empty SYNTH_BLACKBOXES unsupported with HDL frontend \"verific\"" } + } elseif { [env_var_equals SYNTH_HDL_FRONTEND ghdl] } { + plugin -i ghdl + if { [info exists ::env(VHDL_FILES)] } { + for { set i 0 } { $i < [llength $::env(VHDL_FILES)] } { incr i } { + exec -- ghdl -a [lindex $::env(VHDL_FILES) $i] + } + yosys ghdl $::env(DESIGN_NAME) + } } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { verilog_defaults -push if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index dcfe9d9a2a..6b9681a1db 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -241,7 +241,7 @@ SYNTH_KEEP_MOCKED_MEMORIES: SYNTH_HDL_FRONTEND: description: > Select an alternative language frontend to ingest the design. Available option - is "slang". If the variable is empty, design is read with the Yosys read_verilog + is "slang" for systemverilog or "ghdl" for VHDL files. If the variable is empty, design is read with the Yosys read_verilog command. stages: - synth @@ -847,6 +847,13 @@ VERILOG_DEFINES: Example: `-D HPDCACHE_ASSERT_OFF` stages: - synth +VHDL_FILES: + required: true + description: > + The path to the design VHDL files providing a description + of modules. + stages: + - synth SDC_FILE: required: true description: |