From a2ffb3bf9b7cbb58669e7190e8f8cac363bd4afe Mon Sep 17 00:00:00 2001 From: Ashnaa Seth Date: Mon, 13 Apr 2026 17:46:49 +0000 Subject: [PATCH 1/2] rtl: fix missing reset on wden_p in WDT32 wden_p lacked an async reset, causing a simulation/synthesis mismatch: WDOV could be driven X in simulation immediately after reset deassertion when WDEN is asserted. Signed-off-by: Ashnaa Seth Signed-off-by: ashnaaseth2325-oss --- flow/designs/src/chameleon/IPs/WDT32.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/flow/designs/src/chameleon/IPs/WDT32.v b/flow/designs/src/chameleon/IPs/WDT32.v index 3eeea1eeab..dbc00fa56f 100644 --- a/flow/designs/src/chameleon/IPs/WDT32.v +++ b/flow/designs/src/chameleon/IPs/WDT32.v @@ -40,8 +40,9 @@ module WDT32 ( end reg wden_p; - always @(posedge clk) - wden_p <= WDEN; + always @(posedge clk or posedge rst) + if (rst) wden_p <= 1'b0; + else wden_p <= WDEN; always @(posedge clk or posedge rst) begin From d2f1f4137586371f725bc8b85310272623f80491 Mon Sep 17 00:00:00 2001 From: Ashnaa Seth Date: Mon, 13 Apr 2026 18:30:27 +0000 Subject: [PATCH 2/2] WDT32: apply reset fix to duplicated hierarchical IP module Signed-off-by: Ashnaa Seth Signed-off-by: ashnaaseth2325-oss --- .gitmodules | 2 +- flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v | 5 +++-- tools/OpenROAD | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index 32bdbc7301..3bc26810d5 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = ../../The-OpenROAD-Project/yosys.git [submodule "tools/OpenROAD"] path = tools/OpenROAD - url = ../OpenROAD.git + url = https://github.com/The-OpenROAD-Project/OpenROAD.git [submodule "tools/yosys-slang"] path = tools/yosys-slang url = https://github.com/povik/yosys-slang.git diff --git a/flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v b/flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v index 3eeea1eeab..a61d732842 100644 --- a/flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v +++ b/flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v @@ -40,8 +40,9 @@ module WDT32 ( end reg wden_p; - always @(posedge clk) - wden_p <= WDEN; + always @(posedge clk or posedge rst) + if (rst) wden_p <= 1'b0; + else wden_p <= WDEN; always @(posedge clk or posedge rst) begin diff --git a/tools/OpenROAD b/tools/OpenROAD index 0d9d73ffba..0e2d771c5e 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 0d9d73ffba0228f1a7263953fb9b41de800ba301 +Subproject commit 0e2d771c5ec38f232493c2afea738ea0200cb972