diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 42edd07a04..70496ff923 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -55,6 +55,7 @@ #include "sta/Vector.hh" #include "stt/SteinerTreeBuilder.h" #include "utl/Logger.h" +#include "utl/timer.h" namespace cts { @@ -85,6 +86,7 @@ TritonCTS::~TritonCTS() void TritonCTS::runTritonCts() { + utl::Timer timer; odb::dbChip* chip = db_->getChip(); odb::dbBlock* block = chip->getBlock(); options_->addOwner(block); @@ -121,6 +123,7 @@ void TritonCTS::runTritonCts() regTreeRootBufIndex_ = 0; delayBufIndex_ = 0; options_->removeOwner(); + logger_->info(CTS, 500, "Runtime: {:.2f}s", timer.elapsed()); } TreeBuilder* TritonCTS::addBuilder(CtsOptions* options, diff --git a/src/dpl/src/Opendp.cpp b/src/dpl/src/Opendp.cpp index 8a2c1f952d..35707f5282 100644 --- a/src/dpl/src/Opendp.cpp +++ b/src/dpl/src/Opendp.cpp @@ -29,6 +29,7 @@ #include "odb/util.h" #include "util/journal.h" #include "utl/Logger.h" +#include "utl/timer.h" namespace dpl { @@ -117,6 +118,7 @@ void Opendp::detailedPlacement(const int max_displacement_x, const std::string& report_file_name, bool incremental) { + utl::Timer timer; incremental_ = incremental; importDb(); adjustNodesOrient(); @@ -162,6 +164,7 @@ void Opendp::detailedPlacement(const int max_displacement_x, } logger_->error(DPL, 36, "Detailed placement failed."); } + logger_->info(DPL, 500, "Runtime: {:.2f}s", timer.elapsed()); } void Opendp::updateDbInstLocations() diff --git a/src/drt/src/TritonRoute.cpp b/src/drt/src/TritonRoute.cpp index 252d7146a7..6356244dde 100644 --- a/src/drt/src/TritonRoute.cpp +++ b/src/drt/src/TritonRoute.cpp @@ -60,6 +60,7 @@ #include "utl/CallBackHandler.h" #include "utl/Logger.h" #include "utl/ScopedTemporaryFile.h" +#include "utl/timer.h" using odb::dbTechLayerType; @@ -977,6 +978,7 @@ void TritonRoute::sendDesignUpdates(const std::string& router_cfg_path, int TritonRoute::main() { + utl::Timer timer; // Just to verify that OMP support is compiled in correctly. omp_set_num_threads(2); #pragma omp parallel @@ -1075,6 +1077,7 @@ int TritonRoute::main() if (!router_cfg_->SINGLE_STEP_DR) { endFR(); } + logger_->info(utl::DRT, 501, "Runtime: {:.2f}s", timer.elapsed()); return 0; } diff --git a/src/gpl/src/replace.cpp b/src/gpl/src/replace.cpp index 4b24db144e..eb83becbd7 100644 --- a/src/gpl/src/replace.cpp +++ b/src/gpl/src/replace.cpp @@ -24,6 +24,7 @@ #include "sta/StaMain.hh" #include "timingBase.h" #include "utl/Logger.h" +#include "utl/timer.h" #include "utl/validation.h" namespace gpl { @@ -155,8 +156,10 @@ void Replace::doIncrementalPlace(const int threads, const PlaceOptions& options) void Replace::doPlace(const int threads, const PlaceOptions& options) { + utl::Timer timer; doInitialPlace(threads, options); doNesterovPlace(threads, options); + log_->info(GPL, 500, "Runtime: {:.2f}s", timer.elapsed()); } void Replace::doInitialPlace(const int threads, const PlaceOptions& options) diff --git a/src/grt/src/GlobalRouter.cpp b/src/grt/src/GlobalRouter.cpp index b57d47085e..8b5f74b514 100644 --- a/src/grt/src/GlobalRouter.cpp +++ b/src/grt/src/GlobalRouter.cpp @@ -4,7 +4,6 @@ #include "grt/GlobalRouter.h" #include -#include #include #include #include @@ -59,6 +58,7 @@ #include "utl/CallBackHandler.h" #include "utl/Logger.h" #include "utl/algorithms.h" +#include "utl/timer.h" namespace grt { @@ -342,7 +342,7 @@ void GlobalRouter::endIncremental(bool save_guides) void GlobalRouter::globalRoute(bool save_guides) { - auto start = std::chrono::steady_clock::now(); + utl::Timer timer; bool has_routable_nets = false; for (auto net : db_->getChip()->getBlock()->getNets()) { @@ -389,13 +389,11 @@ void GlobalRouter::globalRoute(bool save_guides) } finishGlobalRouting(save_guides); - auto end = std::chrono::steady_clock::now(); if (verbose_) { - auto runtime - = std::chrono::duration_cast(end - start); - int hour = runtime.count() / 3600; - int min = (runtime.count() % 3600) / 60; - int sec = runtime.count() % 60; + const int elapsed = static_cast(timer.elapsed()); + const int hour = elapsed / 3600; + const int min = (elapsed % 3600) / 60; + const int sec = elapsed % 60; logger_->info( GRT, 303, "Global routing runtime = {:02}:{:02}:{:02}", hour, min, sec); } diff --git a/src/ifp/src/InitFloorplan.cc b/src/ifp/src/InitFloorplan.cc index 36c42bfb46..10b22a6cb4 100644 --- a/src/ifp/src/InitFloorplan.cc +++ b/src/ifp/src/InitFloorplan.cc @@ -26,6 +26,7 @@ #include "sta/StringUtil.hh" #include "upf/upf.h" #include "utl/Logger.h" +#include "utl/timer.h" #include "utl/validation.h" namespace ifp { @@ -108,6 +109,7 @@ void InitFloorplan::initFloorplan( const std::set& flipped_sites, const int gap) { + utl::Timer timer; checkGap(gap); makeDieUtilization(utilization, @@ -125,6 +127,7 @@ void InitFloorplan::initFloorplan( row_parity, flipped_sites, gap); + logger_->info(IFP, 500, "Runtime: {:.2f}s", timer.elapsed()); } // The base_site determines the single-height rows. For hybrid rows it is @@ -138,10 +141,12 @@ void InitFloorplan::initFloorplan( const std::set& flipped_sites, const int gap) { + utl::Timer timer; checkGap(gap); makeDie(die); makeRows(core, base_site, additional_sites, row_parity, flipped_sites, gap); + logger_->info(IFP, 501, "Runtime: {:.2f}s", timer.elapsed()); } void InitFloorplan::makeDieUtilization(double utilization, diff --git a/src/ifp/test/init_floorplan1.py b/src/ifp/test/init_floorplan1.py index 750a9dfdc6..cb80c10b60 100644 --- a/src/ifp/test/init_floorplan1.py +++ b/src/ifp/test/init_floorplan1.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan2.py b/src/ifp/test/init_floorplan2.py index 9e811a1b15..1903bb48ff 100644 --- a/src/ifp/test/init_floorplan2.py +++ b/src/ifp/test/init_floorplan2.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan3.py b/src/ifp/test/init_floorplan3.py index 52ae20d674..a5044c6982 100644 --- a/src/ifp/test/init_floorplan3.py +++ b/src/ifp/test/init_floorplan3.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan4.py b/src/ifp/test/init_floorplan4.py index cff7c82960..75e6575601 100644 --- a/src/ifp/test/init_floorplan4.py +++ b/src/ifp/test/init_floorplan4.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan5.py b/src/ifp/test/init_floorplan5.py index 4fc38b7c98..51d8e063f9 100644 --- a/src/ifp/test/init_floorplan5.py +++ b/src/ifp/test/init_floorplan5.py @@ -3,7 +3,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan6.py b/src/ifp/test/init_floorplan6.py index 44f4122c99..095a0be760 100644 --- a/src/ifp/test/init_floorplan6.py +++ b/src/ifp/test/init_floorplan6.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan7.py b/src/ifp/test/init_floorplan7.py index 3d9763f887..eaba44a273 100644 --- a/src/ifp/test/init_floorplan7.py +++ b/src/ifp/test/init_floorplan7.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan8.py b/src/ifp/test/init_floorplan8.py index 16cb7a19b0..9a2acfd6e0 100644 --- a/src/ifp/test/init_floorplan8.py +++ b/src/ifp/test/init_floorplan8.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan9.py b/src/ifp/test/init_floorplan9.py index c4f6c8e5e5..ee86375d5e 100644 --- a/src/ifp/test/init_floorplan9.py +++ b/src/ifp/test/init_floorplan9.py @@ -7,7 +7,7 @@ tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef") tech.readLiberty("sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg2.v") design.link("top") diff --git a/src/ifp/test/init_floorplan_dbl_row.py b/src/ifp/test/init_floorplan_dbl_row.py index d9d7e43372..1e28e8cd24 100644 --- a/src/ifp/test/init_floorplan_dbl_row.py +++ b/src/ifp/test/init_floorplan_dbl_row.py @@ -8,7 +8,7 @@ tech.readLef("init_floorplan_dbl_row.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan_flip_sites.py b/src/ifp/test/init_floorplan_flip_sites.py index c278ff0582..0797b1f2ad 100644 --- a/src/ifp/test/init_floorplan_flip_sites.py +++ b/src/ifp/test/init_floorplan_flip_sites.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/init_floorplan_gap.py b/src/ifp/test/init_floorplan_gap.py index 6516bfcbc6..84ca384399 100644 --- a/src/ifp/test/init_floorplan_gap.py +++ b/src/ifp/test/init_floorplan_gap.py @@ -8,7 +8,7 @@ tech.readLef("init_floorplan_gap.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks1.py b/src/ifp/test/make_tracks1.py index de3ddad4fc..27dea294ab 100644 --- a/src/ifp/test/make_tracks1.py +++ b/src/ifp/test/make_tracks1.py @@ -5,7 +5,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks2.py b/src/ifp/test/make_tracks2.py index 7906693c5c..4c4dde73cf 100644 --- a/src/ifp/test/make_tracks2.py +++ b/src/ifp/test/make_tracks2.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks3.py b/src/ifp/test/make_tracks3.py index 27700eb97f..d8c6e09ce2 100644 --- a/src/ifp/test/make_tracks3.py +++ b/src/ifp/test/make_tracks3.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks4.py b/src/ifp/test/make_tracks4.py index d1bb62d494..c940fb76f5 100644 --- a/src/ifp/test/make_tracks4.py +++ b/src/ifp/test/make_tracks4.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks5.py b/src/ifp/test/make_tracks5.py index 135e63f807..71b2bd5dee 100644 --- a/src/ifp/test/make_tracks5.py +++ b/src/ifp/test/make_tracks5.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/make_tracks6.py b/src/ifp/test/make_tracks6.py index b3adc9c032..ea6d6901ba 100644 --- a/src/ifp/test/make_tracks6.py +++ b/src/ifp/test/make_tracks6.py @@ -6,7 +6,7 @@ tech = Tech() tech.readLef("Nangate45/Nangate45.lef") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/manpage.py b/src/ifp/test/manpage.py index c39859549f..f01603ba02 120000 --- a/src/ifp/test/manpage.py +++ b/src/ifp/test/manpage.py @@ -1 +1 @@ -../../../docs/src/scripts/manpage.py \ No newline at end of file +../../../docs/src/scripts/manpage.py diff --git a/src/ifp/test/md_roff_compat.py b/src/ifp/test/md_roff_compat.py index 43530e421e..02f66358ce 120000 --- a/src/ifp/test/md_roff_compat.py +++ b/src/ifp/test/md_roff_compat.py @@ -1 +1 @@ -../../../docs/src/scripts/md_roff_compat.py \ No newline at end of file +../../../docs/src/scripts/md_roff_compat.py diff --git a/src/ifp/test/placement_blockage1.py b/src/ifp/test/placement_blockage1.py index 18db3e982a..0775626b11 100644 --- a/src/ifp/test/placement_blockage1.py +++ b/src/ifp/test/placement_blockage1.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/placement_blockage2.py b/src/ifp/test/placement_blockage2.py index e733ae6a1e..8c9b3d99f9 100644 --- a/src/ifp/test/placement_blockage2.py +++ b/src/ifp/test/placement_blockage2.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("reg1.v") design.link("top") diff --git a/src/ifp/test/tiecells.py b/src/ifp/test/tiecells.py index 6f3828b9e4..3c335a8f21 100644 --- a/src/ifp/test/tiecells.py +++ b/src/ifp/test/tiecells.py @@ -7,7 +7,7 @@ tech.readLef("Nangate45/Nangate45.lef") tech.readLiberty("Nangate45/Nangate45_typ.lib") -design = Design(tech) +design = helpers.make_design(tech) design.readVerilog("tiecells.v") design.link("top") diff --git a/src/mpl/src/rtl_mp.cpp b/src/mpl/src/rtl_mp.cpp index 274684c817..d0bfcd6264 100644 --- a/src/mpl/src/rtl_mp.cpp +++ b/src/mpl/src/rtl_mp.cpp @@ -13,6 +13,7 @@ #include "odb/db.h" #include "odb/geom.h" #include "utl/Logger.h" +#include "utl/timer.h" namespace mpl { using std::string; @@ -58,6 +59,7 @@ bool MacroPlacer::place(const int num_threads, const char* report_directory, const bool keep_clustering_data) { + utl::Timer timer; hier_rtlmp_->init(); hier_rtlmp_->setClusterSize( max_num_macro, min_num_macro, max_num_inst, min_num_inst); @@ -84,6 +86,7 @@ bool MacroPlacer::place(const int num_threads, hier_rtlmp_->run(); + logger_->info(MPL, 500, "Runtime: {:.2f}s", timer.elapsed()); return true; } diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index 9b52bbe139..a9126336bf 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -89,6 +89,7 @@ #include "utl/Logger.h" #include "utl/algorithms.h" #include "utl/scope.h" +#include "utl/timer.h" // http://vlsicad.eecs.umich.edu/BK/Slots/cache/dropzone.tamu.edu/~zhuoli/GSRC/fast_buffer_insertion.html @@ -4223,6 +4224,7 @@ void Resizer::repairDesign(double max_wire_length, bool match_cell_footprint, bool verbose) { + utl::Timer timer; utl::SetAndRestore set_match_footprint(match_cell_footprint_, match_cell_footprint); resizePreamble(); @@ -4234,6 +4236,7 @@ void Resizer::repairDesign(double max_wire_length, } repair_design_->repairDesign( max_wire_length, slew_margin, cap_margin, buffer_gain, verbose); + logger_->info(RSZ, 500, "Runtime: {:.2f}s", timer.elapsed()); } int Resizer::repairDesignBufferCount() const diff --git a/test/helpers.py b/test/helpers.py index 41c91212d7..8519f90bde 100644 --- a/test/helpers.py +++ b/test/helpers.py @@ -116,4 +116,14 @@ def make_design(tech): logger.suppressMessage(utl.GRT, 303) logger.suppressMessage(utl.GRT, 704) + # suppress elapsed time messages (non-deterministic) + logger.suppressMessage(utl.CTS, 500) + logger.suppressMessage(utl.DPL, 500) + logger.suppressMessage(utl.DRT, 501) + logger.suppressMessage(utl.GPL, 500) + logger.suppressMessage(utl.IFP, 500) + logger.suppressMessage(utl.IFP, 501) + logger.suppressMessage(utl.MPL, 500) + logger.suppressMessage(utl.RSZ, 500) + return design diff --git a/test/helpers.tcl b/test/helpers.tcl index 9f20444246..577880e9e5 100644 --- a/test/helpers.tcl +++ b/test/helpers.tcl @@ -297,6 +297,16 @@ suppress_message ORD 30 suppress_message GRT 303 suppress_message GRT 704 +# suppress elapsed time messages (non-deterministic) +suppress_message CTS 500 +suppress_message DPL 500 +suppress_message DRT 501 +suppress_message GPL 500 +suppress_message IFP 500 +suppress_message IFP 501 +suppress_message MPL 500 +suppress_message RSZ 500 + proc get_3dblox_marker_count { category_name } { set top_chip [[ord::get_db] getChip] if { $top_chip == "NULL" } {