sky130 PEX fails due to missing storage node labels in bitcell_2port

[DashCodeHub]

Hi Everyone, I have been trying to experiment with OpenRAM and generate an sram block with the following configuration ⁨:

word_size = 8
num_words = 128

num_rw_ports = 1
num_r_ports  = 1
num_w_ports  = 0

tech_name = "sky130"

check_lvsdrc = True
use_pex = True
pex_name = "magic"

analytical_delay = False
nominal_corner_only = True

num_threads = 64
num_sim_threads = 128
keep_temp = True

Everything was working fine until I enabled :

use_pex=True

With

use_pex = False

generates correctly, DRC=0, LVS matches (just top level not inline) and full characterization comletes. After enabling PEX this the error that I am getting ⁨

ERROR: file geometry.py: line 402: normalized storage nets should not be empty! Check if the GDS labels Q and Q_bar are correctly set on M1 of the cell
Traceback (most recent call last):
  File "/home/uns991/work/OpenRAM/sram_compiler.py", line 73, in <module>
    s = sram()
  File "/home/uns991/work/OpenRAM/compiler/sram.py", line 58, in __init__
    self.s.create_layout()
  File "/home/uns991/work/OpenRAM/compiler/modules/sram_1bank.py", line 231, in create_layout
    self.add_global_pex_labels()
  File "/home/uns991/work/OpenRAM/compiler/modules/sram_1bank.py", line 122, in add_global_pex_labels
    pex_data = bank.reverse_transformation_bitcell(self.bitcell.name)
  File "/home/uns991/work/OpenRAM/compiler/base/geometry.py", line 435, in reverse_transformation_bitcell
    walk_subtree(self)
  File "/home/uns991/work/OpenRAM/compiler/base/geometry.py", line 432, in walk_subtree
    walk_subtree(instance)
  File "/home/uns991/work/OpenRAM/compiler/base/geometry.py", line 432, in walk_subtree
    walk_subtree(instance)
  File "/home/uns991/work/OpenRAM/compiler/base/geometry.py", line 432, in walk_subtree
    walk_subtree(instance)
  [Previous line repeated 1 more time]
  File "/home/uns991/work/OpenRAM/compiler/base/geometry.py", line 402, in walk_subtree
    debug.error("normalized storage nets should not be empty! Check if the GDS labels Q and Q_bar are correctly set on M1 of the cell",1)
  File "/home/uns991/work/OpenRAM/compiler/debug.py", line 48, in error
    assert return_value == 0
AssertionError

⁩ (I have attached the logfile generated by OpenRAM). Traceback originates from: ⁨

add_global_pex_labels()
reverse_transformation_bitcell()

Bitcell used by OpenRAM

uns991@lucent-loka:~/work/OpenRAM$ grep -R "bitcell_2port" technology/sky130/tech/tech.py
tech_modules["replica_bitcell_2port"] = "replica_bitcell_2port"
tech_modules["dummy_bitcell_2port"] = "dummy_bitcell_2port"
tech_modules["bitcell_2port"] = "bitcell_2port"
tech_modules["col_cap"] = ["sky130_col_cap", "col_cap_bitcell_2port"]
tech_modules["row_cap"] = ["sky130_row_cap", "row_cap_bitcell_2port"]
cell_properties.bitcell_2port.mirror.x = True
cell_properties.bitcell_2port.mirror.y = True
cell_properties.bitcell_2port.end_caps = True
cell_properties.bitcell_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd']
cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
cell_properties.bitcell_2port.wl_layer = "m2"
cell_properties.bitcell_2port.vdd_layer = "m1"
cell_properties.bitcell_2port.vdd_dir = "H"
cell_properties.bitcell_2port.gnd_layer = "m2"
cell_properties.bitcell_2port.gnd_dir = "H"
cell_properties.names["bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell"
cell_properties.names["dummy_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_dummy"
cell_properties.names["replica_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_replica"
cell_properties.names["col_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_col"
cell_properties.names["row_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_row"

So OpenRAM maps bitcell_2port → sky130_fd_bd_sram__openram_dp_cell and Layout file used

OpenRAM/technology/sky130/mag_lib/sky130_fd_bd_sram__openram_dp_cell.mag

Bitcell label Inspection

Inspecting the label section of the .mag file ⁨

  $0 ~ /^<< labels/ {inlabels=1; print; next}
  $0 ~ /^<< / && inlabels {exit}
  inlabels {print}
' /home/uns991/work/OpenRAM/technology/sky130/mag_lib/sky130_fd_bd_sram__openram_dp_cell.mag
<< labels >>
flabel comment s 32 142 32 142 0 FreeSans 100 0 0 0 short li
flabel comment s 40 159 40 159 0 FreeSans 100 0 0 0 no mcon
flabel comment s 32 180 32 180 0 FreeSans 100 0 0 0 in cell
flabel comment s 240 169 240 169 0 FreeSans 100 0 0 0 
MAIN CELL
flabel comment s 241 150 241 150 0 FreeSans 100 0 0 0 opt.1
flabel comment s 45 57 45 57 0 FreeSans 100 0 0 0 short met1
flabel comment s 43 259 43 259 0 FreeSans 100 0 0 0 short met1
flabel comment s 32 174 32 174 0 FreeSans 100 0 0 0 short li
flabel comment s 40 157 40 157 0 FreeSans 100 0 0 0 no mcon
flabel comment s 32 136 32 136 0 FreeSans 100 0 0 0 in cell
flabel comment s 45 57 45 57 0 FreeSans 100 0 0 0 short met1
flabel comment s 43 259 43 259 0 FreeSans 100 0 0 0 short met1
flabel comment s 32 174 32 174 0 FreeSans 100 0 0 0 short li
flabel comment s 40 157 40 157 0 FreeSans 100 0 0 0 no mcon
flabel comment s 32 136 32 136 0 FreeSans 100 0 0 0 in cell
flabel comment s 45 57 45 57 0 FreeSans 100 0 0 0 short met1
flabel comment s 43 259 43 259 0 FreeSans 100 0 0 0 short met1
flabel comment s 32 174 32 174 0 FreeSans 100 0 0 0 short li
flabel comment s 40 157 40 157 0 FreeSans 100 0 0 0 no mcon
flabel comment s 32 136 32 136 0 FreeSans 100 0 0 0 in cell
flabel comment s 45 57 45 57 0 FreeSans 100 0 0 0 short met1
flabel comment s 43 259 43 259 0 FreeSans 100 0 0 0 short met1
flabel comment s 32 174 32 174 0 FreeSans 100 0 0 0 short li
flabel comment s 40 157 40 157 0 FreeSans 100 0 0 0 no mcon
flabel comment s 32 136 32 136 0 FreeSans 100 0 0 0 in cell
flabel metal2 s 225 222 256 256 0 FreeSans 2000 0 0 0 GND
port 4 nsew
flabel metal2 s 224 -14 255 19 0 FreeSans 2000 0 0 0 GND
port 4 nsew
flabel metal2 s 324 331 355 365 0 FreeSans 2000 0 0 0 WL0
port 6 nsew
flabel metal2 s 303 107 335 141 0 FreeSans 2000 0 0 0 WL1
port 7 nsew
flabel metal1 s 222 112 258 160 0 FreeSans 2000 0 0 0 VDD
port 5 nsew
flabel metal1 s 78 117 114 165 0 FreeSans 2000 0 0 0 BL0
port 0 nsew
flabel metal1 s 294 117 330 165 0 FreeSans 2000 0 0 0 BL1
port 1 nsew
flabel metal1 s 150 117 186 165 0 FreeSans 2000 0 0 0 BR0
port 2 nsew
flabel metal1 s 366 117 402 165 0 FreeSans 2000 0 0 0 BR1
port 3 nsew
uns991@lucent-loka:~/work/OpenRAM$

This shows only port labels BL0, BR0, BL1, BR1, WL0, WL1, VDD, GND. There are no internal storage node labels such as: Q, Q_bar, q/qb .

OpenRAM version

(base) uns991@lucent-loka:~/work/OpenRAM$ python3 sram_compiler.py --version
1.2.49

log file
sram_8x128_1r1rw_v5.log

How to resolve this? Let me know if any other details is needed.

[mguthaus]

This has been a long standing issue that versions of magic will extract differently. Mostly this is due to partial devices that span the bitcell boundary. I'm not sure if this is causing your issue...

[mguthaus]

Ignore the above. We welcome any fixes in a PR.