processor_sim

#! /usr/bin/vvp
:ivl_version "12.0 (stable)" "(v12_0-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/ivl/system.vpi";
:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/ivl/va_math.vpi";
S_0x586394d54920 .scope module, "riscv_4bit_processor_tb" "riscv_4bit_processor_tb" 2 1;
 .timescale 0 0;
v0x586394d8f480_0 .var "clk", 0 0;
v0x586394d8f520_0 .var "reset", 0 0;
v0x586394d8f5e0_0 .net "result", 3 0, L_0x586394d8ffc0;  1 drivers
S_0x586394d5d520 .scope module, "dut" "riscv_4bit_processor" 2 8, 3 1 0, S_0x586394d54920;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /OUTPUT 4 "result";
L_0x586394d8ffc0 .functor BUFZ 4, v0x586394d8c280_0, C4<0000>, C4<0000>, C4<0000>;
v0x586394d8e7f0_0 .net "alu_op", 0 0, v0x586394d8c670_0;  1 drivers
v0x586394d8e8b0_0 .net "alu_result", 3 0, v0x586394d8c280_0;  1 drivers
v0x586394d8e9c0_0 .net "clk", 0 0, v0x586394d8f480_0;  1 drivers
v0x586394d8eab0_0 .net "instruction", 11 0, v0x586394d8cbb0_0;  1 drivers
v0x586394d8eba0_0 .net "pc", 3 0, v0x586394d8d3a0_0;  1 drivers
v0x586394d8ed00_0 .net "rd_addr", 1 0, L_0x586394d8f8f0;  1 drivers
v0x586394d8edc0_0 .net "reg_we", 0 0, v0x586394d8c890_0;  1 drivers
v0x586394d8eeb0_0 .net "reset", 0 0, v0x586394d8f520_0;  1 drivers
v0x586394d8efa0_0 .net "result", 3 0, L_0x586394d8ffc0;  alias, 1 drivers
v0x586394d8f0f0_0 .net "rs1_addr", 1 0, L_0x586394d8f680;  1 drivers
v0x586394d8f1b0_0 .net "rs1_data", 3 0, L_0x586394d8fc10;  1 drivers
v0x586394d8f250_0 .net "rs2_addr", 1 0, L_0x586394d8f770;  1 drivers
v0x586394d8f310_0 .net "rs2_data", 3 0, L_0x586394d8ff00;  1 drivers
L_0x586394d8f680 .part v0x586394d8cbb0_0, 2, 2;
L_0x586394d8f770 .part v0x586394d8cbb0_0, 4, 2;
L_0x586394d8f8f0 .part v0x586394d8cbb0_0, 6, 2;
S_0x586394d5d6b0 .scope module, "alu_inst" "alu" 3 53, 4 1 0, S_0x586394d5d520;
 .timescale 0 0;
    .port_info 0 /INPUT 4 "a";
    .port_info 1 /INPUT 4 "b";
    .port_info 2 /INPUT 1 "opcode";
    .port_info 3 /OUTPUT 4 "result";
v0x586394d526d0_0 .net "a", 3 0, L_0x586394d8fc10;  alias, 1 drivers
v0x586394d52770_0 .net "b", 3 0, L_0x586394d8ff00;  alias, 1 drivers
v0x586394d8c1e0_0 .net "opcode", 0 0, v0x586394d8c670_0;  alias, 1 drivers
v0x586394d8c280_0 .var "result", 3 0;
E_0x586394d664e0 .event anyedge, v0x586394d8c1e0_0, v0x586394d526d0_0, v0x586394d52770_0;
S_0x586394d8c3e0 .scope module, "cu" "control_unit" 3 33, 5 1 0, S_0x586394d5d520;
 .timescale 0 0;
    .port_info 0 /INPUT 12 "instruction";
    .port_info 1 /OUTPUT 1 "alu_op";
    .port_info 2 /OUTPUT 1 "reg_we";
v0x586394d8c670_0 .var "alu_op", 0 0;
v0x586394d8c730_0 .net "instruction", 11 0, v0x586394d8cbb0_0;  alias, 1 drivers
v0x586394d8c7f0_0 .net "opcode", 0 0, L_0x586394d8f990;  1 drivers
v0x586394d8c890_0 .var "reg_we", 0 0;
E_0x586394d43250 .event anyedge, v0x586394d8c7f0_0;
L_0x586394d8f990 .part v0x586394d8cbb0_0, 0, 1;
S_0x586394d8c9d0 .scope module, "imem" "instruction_memory" 3 27, 6 1 0, S_0x586394d5d520;
 .timescale 0 0;
    .port_info 0 /INPUT 4 "pc";
    .port_info 1 /OUTPUT 12 "instr";
v0x586394d8cbb0_0 .var "instr", 11 0;
v0x586394d8cc90 .array "mem", 15 0, 11 0;
v0x586394d8cf30_0 .net "pc", 3 0, v0x586394d8d3a0_0;  alias, 1 drivers
v0x586394d8cc90_0 .array/port v0x586394d8cc90, 0;
v0x586394d8cc90_1 .array/port v0x586394d8cc90, 1;
v0x586394d8cc90_2 .array/port v0x586394d8cc90, 2;
E_0x586394d56780/0 .event anyedge, v0x586394d8cf30_0, v0x586394d8cc90_0, v0x586394d8cc90_1, v0x586394d8cc90_2;
v0x586394d8cc90_3 .array/port v0x586394d8cc90, 3;
v0x586394d8cc90_4 .array/port v0x586394d8cc90, 4;
v0x586394d8cc90_5 .array/port v0x586394d8cc90, 5;
v0x586394d8cc90_6 .array/port v0x586394d8cc90, 6;
E_0x586394d56780/1 .event anyedge, v0x586394d8cc90_3, v0x586394d8cc90_4, v0x586394d8cc90_5, v0x586394d8cc90_6;
v0x586394d8cc90_7 .array/port v0x586394d8cc90, 7;
v0x586394d8cc90_8 .array/port v0x586394d8cc90, 8;
v0x586394d8cc90_9 .array/port v0x586394d8cc90, 9;
v0x586394d8cc90_10 .array/port v0x586394d8cc90, 10;
E_0x586394d56780/2 .event anyedge, v0x586394d8cc90_7, v0x586394d8cc90_8, v0x586394d8cc90_9, v0x586394d8cc90_10;
v0x586394d8cc90_11 .array/port v0x586394d8cc90, 11;
v0x586394d8cc90_12 .array/port v0x586394d8cc90, 12;
v0x586394d8cc90_13 .array/port v0x586394d8cc90, 13;
v0x586394d8cc90_14 .array/port v0x586394d8cc90, 14;
E_0x586394d56780/3 .event anyedge, v0x586394d8cc90_11, v0x586394d8cc90_12, v0x586394d8cc90_13, v0x586394d8cc90_14;
v0x586394d8cc90_15 .array/port v0x586394d8cc90, 15;
E_0x586394d56780/4 .event anyedge, v0x586394d8cc90_15;
E_0x586394d56780 .event/or E_0x586394d56780/0, E_0x586394d56780/1, E_0x586394d56780/2, E_0x586394d56780/3, E_0x586394d56780/4;
S_0x586394d8d050 .scope module, "pc_inst" "program_counter" 3 20, 7 1 0, S_0x586394d5d520;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /OUTPUT 4 "pc";
v0x586394d8d2c0_0 .net "clk", 0 0, v0x586394d8f480_0;  alias, 1 drivers
v0x586394d8d3a0_0 .var "pc", 3 0;
v0x586394d8d490_0 .net "reset", 0 0, v0x586394d8f520_0;  alias, 1 drivers
E_0x586394d567c0 .event posedge, v0x586394d8d490_0, v0x586394d8d2c0_0;
S_0x586394d8d5c0 .scope module, "regfile" "register_file" 3 40, 8 1 0, S_0x586394d5d520;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "reset";
    .port_info 2 /INPUT 1 "we";
    .port_info 3 /INPUT 2 "rs1_addr";
    .port_info 4 /INPUT 2 "rs2_addr";
    .port_info 5 /INPUT 2 "rd_addr";
    .port_info 6 /INPUT 4 "rd_data";
    .port_info 7 /OUTPUT 4 "rs1_data";
    .port_info 8 /OUTPUT 4 "rs2_data";
L_0x586394d8fc10 .functor BUFZ 4, L_0x586394d8fa30, C4<0000>, C4<0000>, C4<0000>;
L_0x586394d8ff00 .functor BUFZ 4, L_0x586394d8fcf0, C4<0000>, C4<0000>, C4<0000>;
v0x586394d8d920_0 .net *"_ivl_0", 3 0, L_0x586394d8fa30;  1 drivers
v0x586394d8da00_0 .net *"_ivl_10", 3 0, L_0x586394d8fd90;  1 drivers
L_0x73584aa92060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x586394d8dae0_0 .net *"_ivl_13", 1 0, L_0x73584aa92060;  1 drivers
v0x586394d8dba0_0 .net *"_ivl_2", 3 0, L_0x586394d8fad0;  1 drivers
L_0x73584aa92018 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x586394d8dc80_0 .net *"_ivl_5", 1 0, L_0x73584aa92018;  1 drivers
v0x586394d8ddb0_0 .net *"_ivl_8", 3 0, L_0x586394d8fcf0;  1 drivers
v0x586394d8de90_0 .net "clk", 0 0, v0x586394d8f480_0;  alias, 1 drivers
v0x586394d8df30_0 .net "rd_addr", 1 0, L_0x586394d8f8f0;  alias, 1 drivers
v0x586394d8dff0_0 .net "rd_data", 3 0, v0x586394d8c280_0;  alias, 1 drivers
v0x586394d8e170 .array "registers", 3 0, 3 0;
v0x586394d8e210_0 .net "reset", 0 0, v0x586394d8f520_0;  alias, 1 drivers
v0x586394d8e2e0_0 .net "rs1_addr", 1 0, L_0x586394d8f680;  alias, 1 drivers
v0x586394d8e3a0_0 .net "rs1_data", 3 0, L_0x586394d8fc10;  alias, 1 drivers
v0x586394d8e490_0 .net "rs2_addr", 1 0, L_0x586394d8f770;  alias, 1 drivers
v0x586394d8e550_0 .net "rs2_data", 3 0, L_0x586394d8ff00;  alias, 1 drivers
v0x586394d8e640_0 .net "we", 0 0, v0x586394d8c890_0;  alias, 1 drivers
L_0x586394d8fa30 .array/port v0x586394d8e170, L_0x586394d8fad0;
L_0x586394d8fad0 .concat [ 2 2 0 0], L_0x586394d8f680, L_0x73584aa92018;
L_0x586394d8fcf0 .array/port v0x586394d8e170, L_0x586394d8fd90;
L_0x586394d8fd90 .concat [ 2 2 0 0], L_0x586394d8f770, L_0x73584aa92060;
    .scope S_0x586394d8d050;
T_0 ;
    %wait E_0x586394d567c0;
    %load/vec4 v0x586394d8d490_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v0x586394d8d3a0_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v0x586394d8d3a0_0;
    %addi 1, 0, 4;
    %assign/vec4 v0x586394d8d3a0_0, 0;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_0x586394d8c9d0;
T_1 ;
    %pushi/vec4 288, 0, 12;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 529, 0, 12;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 800, 0, 12;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 3, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 4, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 5, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 6, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 7, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 8, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 9, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 10, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 12, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 13, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 14, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %pushi/vec4 0, 0, 12;
    %ix/load 4, 15, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x586394d8cc90, 4, 0;
    %end;
    .thread T_1;
    .scope S_0x586394d8c9d0;
T_2 ;
    %wait E_0x586394d56780;
    %load/vec4 v0x586394d8cf30_0;
    %pad/u 6;
    %ix/vec4 4;
    %load/vec4a v0x586394d8cc90, 4;
    %store/vec4 v0x586394d8cbb0_0, 0, 12;
    %jmp T_2;
    .thread T_2, $push;
    .scope S_0x586394d8c3e0;
T_3 ;
    %wait E_0x586394d43250;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8c670_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8c890_0, 0, 1;
    %load/vec4 v0x586394d8c7f0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 1;
    %cmp/u;
    %jmp/1 T_3.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 1;
    %cmp/u;
    %jmp/1 T_3.1, 6;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8c670_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8c890_0, 0, 1;
    %jmp T_3.3;
T_3.0 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8c670_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x586394d8c890_0, 0, 1;
    %jmp T_3.3;
T_3.1 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x586394d8c670_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x586394d8c890_0, 0, 1;
    %jmp T_3.3;
T_3.3 ;
    %pop/vec4 1;
    %jmp T_3;
    .thread T_3, $push;
    .scope S_0x586394d8d5c0;
T_4 ;
    %wait E_0x586394d567c0;
    %load/vec4 v0x586394d8e210_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %pushi/vec4 2, 0, 4;
    %ix/load 3, 0, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x586394d8e170, 0, 4;
    %pushi/vec4 0, 0, 4;
    %ix/load 3, 1, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x586394d8e170, 0, 4;
    %pushi/vec4 3, 0, 4;
    %ix/load 3, 2, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x586394d8e170, 0, 4;
    %pushi/vec4 0, 0, 4;
    %ix/load 3, 3, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x586394d8e170, 0, 4;
    %jmp T_4.1;
T_4.0 ;
    %load/vec4 v0x586394d8e640_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.2, 8;
    %load/vec4 v0x586394d8dff0_0;
    %load/vec4 v0x586394d8df30_0;
    %pad/u 4;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x586394d8e170, 0, 4;
T_4.2 ;
T_4.1 ;
    %jmp T_4;
    .thread T_4;
    .scope S_0x586394d5d6b0;
T_5 ;
    %wait E_0x586394d664e0;
    %load/vec4 v0x586394d8c1e0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 1;
    %cmp/u;
    %jmp/1 T_5.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 1;
    %cmp/u;
    %jmp/1 T_5.1, 6;
    %pushi/vec4 0, 0, 4;
    %store/vec4 v0x586394d8c280_0, 0, 4;
    %jmp T_5.3;
T_5.0 ;
    %load/vec4 v0x586394d526d0_0;
    %load/vec4 v0x586394d52770_0;
    %add;
    %store/vec4 v0x586394d8c280_0, 0, 4;
    %jmp T_5.3;
T_5.1 ;
    %load/vec4 v0x586394d526d0_0;
    %load/vec4 v0x586394d52770_0;
    %sub;
    %store/vec4 v0x586394d8c280_0, 0, 4;
    %jmp T_5.3;
T_5.3 ;
    %pop/vec4 1;
    %jmp T_5;
    .thread T_5, $push;
    .scope S_0x586394d54920;
T_6 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8f480_0, 0, 1;
T_6.0 ;
    %delay 5, 0;
    %load/vec4 v0x586394d8f480_0;
    %inv;
    %store/vec4 v0x586394d8f480_0, 0, 1;
    %jmp T_6.0;
    %end;
    .thread T_6;
    .scope S_0x586394d54920;
T_7 ;
    %vpi_call 2 22 "$dumpfile", "processor.vcd" {0 0 0};
    %vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x586394d54920 {0 0 0};
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x586394d8f520_0, 0, 1;
    %delay 10, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x586394d8f520_0, 0, 1;
    %delay 40, 0;
    %delay 1, 0;
    %vpi_call 2 35 "$display", "Final Result: %d", v0x586394d8f5e0_0 {0 0 0};
    %load/vec4 v0x586394d8f5e0_0;
    %cmpi/e 0, 0, 4;
    %jmp/0xz  T_7.0, 6;
    %vpi_call 2 39 "$display", "Test Passed!" {0 0 0};
    %jmp T_7.1;
T_7.0 ;
    %vpi_call 2 41 "$display", "Test Failed! Expected 0, got %d", v0x586394d8f5e0_0 {0 0 0};
T_7.1 ;
    %vpi_call 2 43 "$finish" {0 0 0};
    %end;
    .thread T_7;
    .scope S_0x586394d54920;
T_8 ;
    %vpi_call 2 48 "$monitor", "Time=%0t: PC=%d, Result=%d", $time, v0x586394d8eba0_0, v0x586394d8f5e0_0 {0 0 0};
    %end;
    .thread T_8;
# The file index is used to find the file name in the following table.
:file_names 9;
    "N/A";
    "<interactive>";
    "riscv_4bit_processor_tb.v";
    "riscv_4bit_processor.v";
    "alu.v";
    "control_unit.v";
    "instruction_mem.v";
    "program_counter.v";
    "register.v";