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| 1 | +--- |
| 2 | +layout: default |
| 3 | +title: Binary Blobs |
| 4 | +permalink: /Binary-Blobs/ |
| 5 | +nav_order: 3 |
| 6 | +parent: Development |
| 7 | +--- |
| 8 | + |
| 9 | +<!-- markdownlint-disable MD033 --> |
| 10 | +<details open markdown="block"> |
| 11 | + <summary> |
| 12 | + Table of contents |
| 13 | + </summary> |
| 14 | + {: .text-delta } |
| 15 | +1. TOC |
| 16 | +{:toc} |
| 17 | +</details> |
| 18 | +<!-- markdownlint-enable MD033 --> |
| 19 | + |
| 20 | +Coreboot specs |
| 21 | +=== |
| 22 | + |
| 23 | +Intel |
| 24 | +==== |
| 25 | + |
| 26 | +- xxx0: [gm45 bridge, Montevina: no FSP, no ME: X200, T400, T500, R500, X300](https://doc.coreboot.org/mainboard/lenovo/montevina_series.html) : **no QubesOS support there** (no proper vt-d2) |
| 27 | +- [xx20](https://doc.coreboot.org/mainboard/lenovo/x2xx_series.html): [Sandy bridge, no FSP. ME<10: BUP module required only: X220/T420/T520](https://doc.coreboot.org/mainboard/lenovo/Sandy_Bridge_series.html) |
| 28 | +- xx30: [Ivy bridge, no FSP. ME<10: ROMP and BUP required: X230/T430/W530](https://doc.coreboot.org/mainboard/lenovo/Ivy_Bridge_series.html) Z220 CMT and others |
| 29 | + |
| 30 | +Additional required Intel blobs: |
| 31 | +===== |
| 32 | + |
| 33 | +- [FSP is present in all Broadwell+ platforms](https://doc.coreboot.org/soc/intel/fsp/index.html) |
| 34 | + |
| 35 | +ME status on different boards models |
| 36 | +===== |
| 37 | + |
| 38 | +- [Removed in ME <=6 (xxx0)](https://libreboot.org/faq.html#intelme) |
| 39 | +- [Deactivated+Neutered ME in ME 6 <= 10 (xx20 BUP/xx30 BUP+ROMP)](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F#me-versions-from-60-nehalem-to-10x-broadwell-1) |
| 40 | +- [Deactivate+Partially Neutered (BUP, RBE, Kernel and syslibs modules **REQUIRED** in ME > 11)](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F#me-versions-from-11x-skylake-1) |
| 41 | +- [Soft disable/HAP disable bit possible on ME 12+ (**PoC BE CAUTIOUS**)](https://github.com/corna/me_cleaner/pull/384) |
| 42 | +- [xx30, xx20](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F#me-versions-from-60-nehalem-to-10x-broadwell): ME 6 <= 10 |
| 43 | +- [Skylake, Kabylake, Whiskeylake and newer](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F#me-versions-from-11x-skylake): ME >= 11 |
| 44 | +- Intel ME then changed its name to Converged Security Management Engine (CSME), where HAP bit can be flipped, but modules cannot be removed anymore. |
| 45 | + |
| 46 | +AMD |
| 47 | +==== |
| 48 | + |
| 49 | +- [AMD fam15h](https://doc.coreboot.org/soc/amd/family15h.html?highlight=amd) (**eg: kgpe-d16**) |
| 50 | +- [PSP in all models after fam15h](https://doc.coreboot.org/soc/amd/psp_integration.html) |
| 51 | + |
| 52 | +Power9 |
| 53 | +==== |
| 54 | + |
| 55 | +- Blobless. |
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