diff --git a/hw/top_chip/dv/mocha_sim_cfgs.hjson b/hw/top_chip/dv/mocha_sim_cfgs.hjson index ac4878539..2097227ad 100644 --- a/hw/top_chip/dv/mocha_sim_cfgs.hjson +++ b/hw/top_chip/dv/mocha_sim_cfgs.hjson @@ -26,7 +26,7 @@ "{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson", "{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson", "{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson", - "{proj_root}/hw/top_chip/tmp_sim_cfg/i2c_sim_cfg.hjson", + "{proj_root}/hw/top_chip/ip/i2c/dv/i2c_sim_cfg.hjson", "{proj_root}/hw/top_chip/tmp_sim_cfg/gpio_sim_cfg.hjson", "{proj_root}/hw/top_chip/tmp_sim_cfg/rom_ctrl_32kB_sim_cfg.hjson", "{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson", diff --git a/hw/top_chip/tmp_sim_cfg/i2c_sim_cfg.hjson b/hw/top_chip/tmp_sim_cfg/i2c_sim_cfg.hjson deleted file mode 100644 index 392075c69..000000000 --- a/hw/top_chip/tmp_sim_cfg/i2c_sim_cfg.hjson +++ /dev/null @@ -1,327 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - // Name of the sim cfg - typically same as the name of the DUT. - name: i2c - - // Top level dut name (sv module). - dut: i2c - - // Top level testbench name (sv module). - tb: tb - - // Simulator used to sign off this block - tool: xcelium - - // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:dv:i2c_sim:0.1 - - // Testplan hjson file. - testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson" - - // RAL spec - used to generate the RAL model. - ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson" - - // Import additional common sim cfg files. - import_cfgs: [// Project wide common sim cfg file - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson", - // Common CIP test lists - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson", - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson", - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson", - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson", - "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"] - - // Add additional tops for simulation. - sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"] - - // Add coverage exclusion file - vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"] - - // Default iterations for all tests - each test entry can override this. - reseed: 50 - - // Default UVM test and seq class name. - uvm_test: i2c_base_test - uvm_test_seq: i2c_base_vseq - - // Enable cdc instrumentation. - run_opts: ["+cdc_instrumentation_enabled=1"] - - // override VCS config file to disable coverage on testbench module i2c_protocol_cov - overrides: [ - { - name: default_vcs_cov_cfg_file - value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg" - } - ] - - // List of test specifications. - tests: [ - { - name: i2c_host_smoke - uvm_test_seq: i2c_host_smoke_vseq - } - - { - name: i2c_host_override - uvm_test_seq: i2c_host_override_vseq - } - - // TODO(#21887) Removed pending DV fixes after removal - // of double-counted 't_f' - // { - // name: i2c_host_rx_oversample - // uvm_test_seq: i2c_host_rx_oversample_vseq - // run_opts: ["+test_timeout_ns=80_000_000"] - // } - - { - name: i2c_host_fifo_watermark - uvm_test_seq: i2c_host_fifo_watermark_vseq - } - - { - name: i2c_host_fifo_overflow - uvm_test_seq: i2c_host_fifo_overflow_vseq - } - - { - name: i2c_host_fifo_reset_fmt - uvm_test_seq: i2c_host_fifo_reset_fmt_vseq - run_opts: ["+test_timeout_ns=10_000_000"] - } - - { - name: i2c_host_fifo_fmt_empty - uvm_test_seq: i2c_host_fifo_fmt_empty_vseq - run_opts: ["+test_timeout_ns=10_000_000"] - } - - { - name: i2c_host_fifo_reset_rx - uvm_test_seq: i2c_host_fifo_reset_rx_vseq - run_opts: ["+test_timeout_ns=10_000_000"] - } - - { - name: i2c_host_fifo_full - uvm_test_seq: i2c_host_fifo_full_vseq - } - - { - name: i2c_host_perf - uvm_test_seq: i2c_host_perf_vseq - } - - { - name: i2c_host_perf_precise - uvm_test_seq: i2c_host_perf_precise_vseq - } - - { - name: i2c_host_stretch_timeout - uvm_test_seq: i2c_host_stretch_timeout_vseq - } - - { - name: i2c_host_error_intr - uvm_test_seq: i2c_host_error_intr_vseq - } - - { - name: i2c_host_stress_all - uvm_test_seq: i2c_host_stress_all_vseq - } - { - name: i2c_target_glitch - uvm_test_seq: i2c_glitch_vseq - run_opts: ["+i2c_agent_mode=Host", "+en_scb=0"] - reseed: 2 // Directed testcase - } - { - name: i2c_target_smoke - uvm_test_seq: i2c_target_smoke_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=100_000_000"] - } - { - name: i2c_target_stress_wr - uvm_test_seq: i2c_target_stress_wr_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=600_000_000"] - } - { - name: i2c_target_stress_rd - uvm_test_seq: i2c_target_stress_rd_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=100_000_000"] - } - { - name: i2c_target_stretch - uvm_test_seq: i2c_target_stretch_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=400_000_000"] - } - { - name: i2c_target_intr_smoke - uvm_test_seq: i2c_target_smoke_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=200_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_intr_stress_wr - uvm_test_seq: i2c_target_stress_wr_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=600_000_000", - "+use_intr_handler=1", "+slow_acq=1"] - } - { - name: i2c_target_timeout - uvm_test_seq: i2c_target_timeout_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=50_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_unexp_stop - uvm_test_seq: i2c_target_ack_stop_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=50_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_fifo_reset_acq - uvm_test_seq: i2c_target_fifo_reset_acq_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_fifo_reset_tx - uvm_test_seq: i2c_target_fifo_reset_tx_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_perf - uvm_test_seq: i2c_target_perf_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_stress_all - uvm_test_seq: i2c_target_stress_all_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=300_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_bad_addr - uvm_test_seq: i2c_target_smoke_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=20_000_000", - "+use_intr_handler=1", "+i2c_bad_addr_pct=50"] - } - { - name: i2c_target_hrst - uvm_test_seq: i2c_target_hrst_vseq - run_opts: ["+i2c_agent_mode=Host", "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: "i2c_host_stress_all_with_rand_reset" - uvm_test_seq: "i2c_common_vseq" - run_opts: ["+run_stress_all_with_rand_reset", - "+stress_seq=i2c_host_stress_all_vseq"] - run_timeout_mins: 20 - reseed: 10 - } - { - name: "i2c_target_stress_all_with_rand_reset" - uvm_test_seq: "i2c_common_vseq" - run_opts: ["+i2c_agent_mode=Host", - "+run_stress_all_with_rand_reset", - "+stress_seq=i2c_target_stress_all_vseq"] - run_timeout_mins: 20 - reseed: 10 - } - { - name: "i2c_host_mode_toggle" - uvm_test_seq: "i2c_host_mode_toggle_vseq" - run_timeout_mins: 10 - } - { - name: "i2c_host_may_nack" - uvm_test_seq: "i2c_host_may_nack_vseq" - } - { - name: i2c_target_fifo_watermarks_acq - uvm_test_seq: i2c_target_fifo_watermarks_acq_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_fifo_watermarks_tx - uvm_test_seq: i2c_target_fifo_watermarks_tx_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_tx_stretch_ctrl - uvm_test_seq: i2c_target_tx_stretch_ctrl_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_smbus_maxlen - uvm_test_seq: i2c_target_smbus_maxlen_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_nack_acqfull - uvm_test_seq: i2c_target_nack_acqfull_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_nack_acqfull_addr - uvm_test_seq: i2c_target_nack_acqfull_addr_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - { - name: i2c_target_nack_txstretch - uvm_test_seq: i2c_target_nack_txstretch_vseq - run_opts: ["+i2c_agent_mode=Host", - "+test_timeout_ns=20_000_000", - "+use_intr_handler=1"] - } - ] - - // List of regressions. - regressions: [ - { - name: smoke - tests: ["i2c_host_smoke"] - } - { - name : host_sanity - tests: ["i2c_host_smoke", "i2c_host_override", "i2c_host_perf", - "i2c_host_fifo_watermark", "i2c_host_fifo_overflow", "i2c_host_fifo_reset_fmt", - "i2c_host_rx_oversample", "i2c_host_stretch_timeout", - "i2c_host_fifo_fmt_empty", "i2c_host_fifo_reset_rx", "i2c_host_stretch_timeout", - "i2c_host_fifo_full", "i2c_host_may_nack", - "i2c_host_error_intr"] - } - { - name: target_sanity - tests: ["i2c_target_smoke", "i2c_target_stress_wr", - "i2c_target_stress_rd", "i2c_target_stretch", - "i2c_target_intr_smoke", "i2c_target_intr_stress_wr", - "i2c_target_timeout", "i2c_target_unexp_stop", - "i2c_target_glitch", "i2c_target_perf", - "i2c_target_fifo_reset_acq", "i2c_target_fifo_reset_tx", - "i2c_target_bad_addr", "i2c_target_hrst", - "i2c_target_smbus_maxlen"] - } - ] -} diff --git a/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson b/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson index 1fc121e26..a6a2c846a 100644 --- a/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson +++ b/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson @@ -3,10 +3,10 @@ // SPDX-License-Identifier: Apache-2.0 { name: "i2c" - import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", - "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", - "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", - "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", "i2c_sec_cm_testplan.hjson"] testpoints: [ //----------------------------------------------- diff --git a/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson b/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson index 392dba0dc..db081a6fd 100644 --- a/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson +++ b/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson @@ -12,32 +12,32 @@ tb: tb // Simulator used to sign off this block - tool: vcs + tool: xcelium // Fusesoc core file used for building the file list. fusesoc_core: lowrisc:dv:i2c_sim:0.1 // Testplan hjson file. - testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson" + testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson" // RAL spec - used to generate the RAL model. - ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson" + ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c.hjson" // Import additional common sim cfg files. import_cfgs: [// Project wide common sim cfg file - "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson", // Common CIP test lists - "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"] // Add additional tops for simulation. sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"] // Add coverage exclusion file - vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"] + vcs_cov_excl_files: ["{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/i2c_cov_excl.el"] // Default iterations for all tests - each test entry can override this. reseed: 50 @@ -53,7 +53,7 @@ overrides: [ { name: default_vcs_cov_cfg_file - value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg" + value: "-cm_hier {proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg+{proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/cov_excl.cfg" } ] diff --git a/hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Paths-and-Tool.patch b/hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Paths-and-Tool.patch new file mode 100644 index 000000000..3f544277c --- /dev/null +++ b/hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Paths-and-Tool.patch @@ -0,0 +1,75 @@ +diff --git a/data/i2c_testplan.hjson b/data/i2c_testplan.hjson +index 1fc121e..a6a2c84 100644 +--- a/data/i2c_testplan.hjson ++++ b/data/i2c_testplan.hjson +@@ -3,10 +3,10 @@ + // SPDX-License-Identifier: Apache-2.0 + { + name: "i2c" +- import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", +- "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", +- "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", +- "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", ++ import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson", ++ "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson", ++ "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson", ++ "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "i2c_sec_cm_testplan.hjson"] + testpoints: [ + //----------------------------------------------- +diff --git a/dv/i2c_sim_cfg.hjson b/dv/i2c_sim_cfg.hjson +index 392dba0..db081a6 100644 +--- a/dv/i2c_sim_cfg.hjson ++++ b/dv/i2c_sim_cfg.hjson +@@ -12,32 +12,32 @@ + tb: tb + + // Simulator used to sign off this block +- tool: vcs ++ tool: xcelium + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:i2c_sim:0.1 + + // Testplan hjson file. +- testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson" ++ testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson" + + // RAL spec - used to generate the RAL model. +- ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson" ++ ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file +- "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists +- "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", +- "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", +- "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", +- "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", +- "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson", ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson", ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson", ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson", ++ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"] + + // Add coverage exclusion file +- vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"] ++ vcs_cov_excl_files: ["{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/i2c_cov_excl.el"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 +@@ -53,7 +53,7 @@ + overrides: [ + { + name: default_vcs_cov_cfg_file +- value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg" ++ value: "-cm_hier {proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg+{proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/cov_excl.cfg" + } + ] + diff --git a/hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Widths.patch b/hw/vendor/patches/lowrisc_ip/i2c/0002-Fix-Widths.patch similarity index 100% rename from hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Widths.patch rename to hw/vendor/patches/lowrisc_ip/i2c/0002-Fix-Widths.patch