From 39ec50689bf02dd624c87a5837f8971454dd8995 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Tue, 24 Mar 2026 14:04:04 +0800 Subject: [PATCH 01/12] FROMLIST: arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Link: https://lore.kernel.org/all/20260324060405.3098891-1-le.qi@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi --- arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 918db56e2bf9a..1cdbd15f2e267 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include / { @@ -1608,6 +1609,20 @@ bias-pull-up; }; + mi2s1_pins: mi2s1-state { + pins = "gpio108", "gpio109", "gpio110", "gpio111"; + function = "mi2s_1"; + drive-strength = <8>; + bias-disable; + }; + + mi2s_mclk: mi2s-mclk-state { + pins = "gpio122"; + function = "mclk2"; + drive-strength = <8>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -5151,6 +5166,45 @@ dma-coherent; }; }; + + gpr: gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1721 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From 45b2f9dd62d58e8f37f1428410fd1ebbc4ea4c2a Mon Sep 17 00:00:00 2001 From: Le Qi Date: Tue, 24 Mar 2026 14:04:05 +0800 Subject: [PATCH 02/12] FROMLIST: arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Link: https://lore.kernel.org/all/20260324060405.3098891-1-le.qi@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Le Qi --- arch/arm64/boot/dts/qcom/talos-evk.dts | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts index af100e22beeec..6352d614e288c 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "talos-evk-som.dtsi" +#include / { model = "Qualcomm QCS615 IQ 615 EVK"; @@ -40,6 +41,46 @@ }; }; + sound { + compatible = "qcom,qcs615-sndcard"; + model = "TALOS-EVK"; + + pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>; + pinctrl-names = "default"; + + pri-mi2s-capture-dai-link { + link-name = "Primary MI2S Capture"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-mi2s-playback-dai-link { + link-name = "Primary MI2S Playback"; + + codec { + sound-dai = <&codec_da7212>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vreg_v1p8_out: regulator-v1p8-out { compatible = "regulator-fixed"; regulator-name = "vreg-v1p8-out"; @@ -109,6 +150,19 @@ }; }; +&i2c5 { + status = "okay"; + + codec_da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <&vreg_v1p8_out>; + VDDIO-supply = <&vreg_v1p8_out>; + VDDMIC-supply = <&vreg_v3p3_out>; + }; +}; + &mdss_dsi0_out { remote-endpoint = <&adv7535_in>; data-lanes = <0 1 2 3>; @@ -124,6 +178,17 @@ status = "okay"; }; +&q6apmbedai { + #address-cells = <1>; + #size-cells = <0>; + + dai@17 { + reg = ; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + }; +}; + &sdhc_2 { pinctrl-0 = <&sdc2_state_on>; pinctrl-1 = <&sdc2_state_off>; From d2ab0c550582bb5ee80356098c110fb4c13a95f3 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 19 Jan 2026 14:24:54 +0530 Subject: [PATCH 03/12] FROMLIST: arm64: dts: qcom: talos: Add EL2 overlay All the existing variants Talos boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Talos IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Link: https://lore.kernel.org/lkml/20260127-talos-el2-overlay-v2-3-b6a2266532c4@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ arch/arm64/boot/dts/qcom/talos-el2.dtso | 25 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2f4694b2d388f..5fdd0395649b3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -137,6 +137,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb + +qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb diff --git a/arch/arm64/boot/dts/qcom/talos-el2.dtso b/arch/arm64/boot/dts/qcom/talos-el2.dtso new file mode 100644 index 0000000000000..f6818c058d724 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-el2.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + + * Talos specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x1720 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x1080 0x0>; +}; + +&venus { + status = "disabled"; +}; From 253ad0352ccd6f5a4426fdf2ddeb6e20024438d5 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Tue, 3 Feb 2026 17:32:31 +0800 Subject: [PATCH 04/12] PENDING: arm64: dts: qcom: talos-evk-som: Enable Adreno 612 GPU Enable GPU for talos-evk-som platform and provide path for zap shader. Signed-off-by: Jie Zhang --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index f877a3e5d0b00..de16916e98f5b 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -317,6 +317,14 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; From fc157d869c10a9787d3bf15ce2d12a41bb3eb8c0 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Feb 2026 19:20:25 +0530 Subject: [PATCH 05/12] FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/20260128062720.437712-2-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 +-- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 12 +-- arch/arm64/boot/dts/qcom/talos.dtsi | 87 +++++++++------------ 3 files changed, 46 insertions(+), 65 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e5ce9a4faa9cb..164e1a6ad6ac2 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -670,11 +670,9 @@ }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_2_hsphy { @@ -686,11 +684,9 @@ }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index de16916e98f5b..7f0e91a3d67a7 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -555,11 +555,9 @@ */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_hsphy { @@ -571,11 +569,9 @@ }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 1cdbd15f2e267..6e372c0e85443 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4956,9 +4956,9 @@ status = "disabled"; }; - usb_1: usb@a6f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4977,52 +4977,47 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + iommus = <&apps_smmu 0x140 0x0>; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; + phys = <&usb_hsphy_1>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&gcc GCC_USB30_PRIM_BCR>; #address-cells = <2>; #size-cells = <2>; ranges; - status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - - iommus = <&apps_smmu 0x140 0x0>; - interrupts = ; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - }; + status = "disabled"; }; - usb_2: usb@a8f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a8f8800 0x0 0x400>; + usb_2: usb@a800000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a800000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>, @@ -5041,18 +5036,24 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; + iommus = <&apps_smmu 0xe0 0x0>; power-domains = <&gcc USB20_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; + phys = <&usb_hsphy_2>; + phy-names = "usb2-phy"; + resets = <&gcc GCC_USB20_SEC_BCR>; qcom,select-utmi-as-pipe-clk; @@ -5061,26 +5062,14 @@ #size-cells = <2>; ranges; - status = "disabled"; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a800000 0x0 0xcd00>; - - iommus = <&apps_smmu 0xe0 0x0>; - interrupts = ; - - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - - maximum-speed = "high-speed"; - }; + status = "disabled"; }; tsens0: thermal-sensor@c263000 { From c20aaa52ef5dd1c9bd5ad93247396eb2ca797671 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Feb 2026 19:22:50 +0530 Subject: [PATCH 06/12] FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are wakeup capable devices USB controllers on talos are wakeup capable. Hence add wakeup-source property to both controller nodes. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/all/20260128062720.437712-3-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6e372c0e85443..858e9d690659b 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -5012,6 +5012,8 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + wakeup-source; + status = "disabled"; }; @@ -5069,6 +5071,8 @@ snps,hird-threshold = /bits/ 8 <0x10>; maximum-speed = "high-speed"; + wakeup-source; + status = "disabled"; }; From 7fa26b6d0b513221f481b55d5b20508297557dc5 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Mar 2026 14:56:11 +0530 Subject: [PATCH 07/12] Revert "FROMLIST: arm64: dts: qcom: talos: Mark usb controllers are wakeup capable devices" This reverts commit 6f583fcc990caa11dcbe54ffd51908f9b6e42a26. Reason for revert: compilation issue due to commit 6f583fcc990caa11dcbe54ffd51908f9b6e42a26. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 858e9d690659b..6e372c0e85443 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -5012,8 +5012,6 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - wakeup-source; - status = "disabled"; }; @@ -5071,8 +5069,6 @@ snps,hird-threshold = /bits/ 8 <0x10>; maximum-speed = "high-speed"; - wakeup-source; - status = "disabled"; }; From d1f799170e75f44a3c971e881a16830553b86ca7 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 13 Mar 2026 14:56:11 +0530 Subject: [PATCH 08/12] Revert "FROMLIST: arm64: dts: qcom: talos: Flatten usb controller nodes" This reverts commit 94c450310e8905d3767414f75c312c42408d9f53. Reason for revert: compilation issue due to mismatch of USB phy node. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 12 ++- arch/arm64/boot/dts/qcom/talos.dtsi | 87 ++++++++++++--------- 3 files changed, 65 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 164e1a6ad6ac2..e5ce9a4faa9cb 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -670,11 +670,13 @@ }; &usb_1 { - dr_mode = "peripheral"; - status = "okay"; }; +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + &usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; @@ -684,11 +686,13 @@ }; &usb_2 { - dr_mode = "host"; - status = "okay"; }; +&usb_2_dwc3 { + dr_mode = "host"; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l17a>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 7f0e91a3d67a7..de16916e98f5b 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -555,11 +555,13 @@ */ &usb_1 { - dr_mode = "host"; - status = "okay"; }; +&usb_1_dwc3 { + dr_mode = "host"; +}; + &usb_1_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; @@ -569,11 +571,13 @@ }; &usb_2 { - dr_mode = "host"; - status = "okay"; }; +&usb_2_dwc3 { + dr_mode = "host"; +}; + &usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6e372c0e85443..1cdbd15f2e267 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4956,9 +4956,9 @@ status = "disabled"; }; - usb_1: usb@a600000 { - compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; - reg = <0x0 0x0a600000 0x0 0xfc100>; + usb_1: usb@a6f8800 { + compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4977,47 +4977,52 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dwc_usb3", - "pwr_event", + interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; - iommus = <&apps_smmu 0x140 0x0>; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&usb_hsphy_1>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - resets = <&gcc GCC_USB30_PRIM_BCR>; #address-cells = <2>; #size-cells = <2>; ranges; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + + iommus = <&apps_smmu 0x140 0x0>; + interrupts = ; + + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + }; }; - usb_2: usb@a800000 { - compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; - reg = <0x0 0x0a800000 0x0 0xfc100>; + usb_2: usb@a8f8800 { + compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a8f8800 0x0 0x400>; clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>, @@ -5036,24 +5041,18 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "dwc_usb3", - "pwr_event", + interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; - iommus = <&apps_smmu 0xe0 0x0>; power-domains = <&gcc USB20_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&usb_hsphy_2>; - phy-names = "usb2-phy"; - resets = <&gcc GCC_USB20_SEC_BCR>; qcom,select-utmi-as-pipe-clk; @@ -5062,14 +5061,26 @@ #size-cells = <2>; ranges; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - maximum-speed = "high-speed"; - status = "disabled"; + + usb_2_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a800000 0x0 0xcd00>; + + iommus = <&apps_smmu 0xe0 0x0>; + interrupts = ; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + + maximum-speed = "high-speed"; + }; }; tsens0: thermal-sensor@c263000 { From 9139256aa1f25dd20ef5b40d540510dec3cfdb3a Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 16 Mar 2026 12:32:42 +0800 Subject: [PATCH 09/12] FROMLIST: arm64: dts: qcom: remove the disabled replicator Remove the disabled device that blocks probing of the connected replicator, as the replicator driver validates all connected devices during probe. kernel log: [ 18.540971] platform 6046000.replicator: deferred probe pending: (reason unknown) Link: https://lore.kernel.org/all/20260316-clean-up-failed-devices-v1-1-f22fc9b072ab@oss.qualcomm.com/ Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/talos.dtsi | 41 ----------------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 1cdbd15f2e267..020005a6eb5fe 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2460,14 +2460,6 @@ remote-endpoint = <&tmc_etr_in>; }; }; - - port@1 { - reg = <1>; - - replicator0_out1: endpoint { - remote-endpoint = <&replicator1_in>; - }; - }; }; }; @@ -2514,31 +2506,6 @@ }; }; - replicator@604a000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x0 0x0604a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - status = "disabled"; - - in-ports { - port { - replicator1_in: endpoint { - remote-endpoint = <&replicator0_out1>; - }; - }; - }; - - out-ports { - port { - replicator1_out: endpoint { - remote-endpoint = <&funnel_swao_in6>; - }; - }; - }; - }; - cti@683b000 { compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x0 0x0683b000 0x0 0x1000>; @@ -2960,14 +2927,6 @@ #address-cells = <1>; #size-cells = <0>; - port@6 { - reg = <6>; - - funnel_swao_in6: endpoint { - remote-endpoint = <&replicator1_out>; - }; - }; - port@7 { reg = <7>; From 80b828e31f511176ca28cc3996ac33ac7ebd9797 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 18:43:20 +0530 Subject: [PATCH 10/12] FROMLIST: arm64: dts: qcom: talos: Add QSPI support The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Link: https://patch.msgid.link/20260324-spi-nor-v1-3-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 020005a6eb5fe..812cd53e93b62 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -532,6 +532,25 @@ }; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-60000000 { + opp-hz = /bits/ 64 <60000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-133250000 { + opp-hz = /bits/ 64 <133250000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; @@ -1623,6 +1642,34 @@ bias-disable; }; + qspi_cs0: qspi-cs0-state { + pins = "gpio44"; + function = "qspi"; + bias-disable; + drive-strength = <6>; + }; + + qspi_data0123: qspi-data0123-state { + pins = "gpio45", "gpio46", "gpio47", "gpio49"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_clk: qspi-clk-state { + pins = "gpio48"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + + qspi_cs1: qspi-cs1-state { + pins = "gpio50"; + function = "qspi"; + bias-pull-down; + drive-strength = <6>; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -3876,6 +3923,39 @@ }; }; + qspi: spi@88df000 { + compatible = "qcom,qcs615-qspi", + "qcom,qspi-v1"; + reg = <0x0 0x088df000 0x0 0x1000>; + + interrupts = ; + + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QSPI QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qspi-config", + "qspi-memory"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qspi_opp_table>; + + iommus = <&apps_smmu 0x160 0x0>; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc"; From 367314f4728d5949e932dad7ca5dbc27d66844a0 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 24 Mar 2026 20:45:34 +0530 Subject: [PATCH 11/12] FROMLIST: arm64: dts: qcom: qcs615-ride: enable QSPI and NOR flash The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Link: https://patch.msgid.link/20260324-spi-nor-v1-4-3efe59c1c119@oss.qualcomm.com Signed-off-by: Viken Dadhaniya --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e5ce9a4faa9cb..addb6e6e66ee4 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -531,6 +531,18 @@ }; }; +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From 5e2a02a91f9225754e8a5b07bae47ab2e7141aca Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 11 Mar 2026 16:05:48 +0530 Subject: [PATCH 12/12] FROMLIST: arm64: dts: qcom: talos: Add clocks for QoS configuration Add clocks which need to be enabled for configuring QoS on talos SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260311103548.1823044-4-odelu.kukatla@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 812cd53e93b62..dd76f6d002705 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1265,6 +1265,10 @@ compatible = "qcom,qcs615-aggre1-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 {