From 9c47fe9517d7e7be00d9ae14b09490d596a98088 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 11 Feb 2026 21:24:23 +0530 Subject: [PATCH 1/3] FROMLIST: net: stmmac: Inverse the phy-mode definition In the initial device tree submission, the definitions of rgmii and rgmii-id in the phy-mode property were inverted compared to the conventions used by the upstream Linux kernel community. Only QCS-EVB-400 and SA8155-ADP platforms are affected due to the incorrect PHY mode configuration: 'rgmii' was used instead of the correct 'rgmii-id'. This change results in an ABI compatibility break, but it is acceptable as these platforms are not actively used by any customers, based on current observations. Qualcomm expects the MAC, not the PHY, to introduce the timing delay, and the driver is designed accordingly. This is due to specific SoC hardware that handles delay and sampling internally. Link: https://lore.kernel.org/netdev/20250819-qcs615_eth-v4-2-5050ed3402cb@oss.qualcomm.com/ Signed-off-by: Yijie Yang Signed-off-by: Mohd Ayaan Anwar --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index d8fd4d8f6ced7..7117559ddaf14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -387,14 +387,11 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) { struct device *dev = ðqos->pdev->dev; - int phase_shift; + int phase_shift = 0; int loopback; /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ - if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || - ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) - phase_shift = 0; - else + if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID) phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; /* Disable loopback mode */ @@ -789,7 +786,14 @@ static int qcom_ethqos_probe(struct platform_device *pdev) if (!ethqos) return -ENOMEM; + /* Qualcomm configures the MAC to introduce delay; instruct the + * PHY not to add additional delay. + */ + if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) + plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII; + ethqos->phy_mode = plat_dat->phy_interface; + switch (ethqos->phy_mode) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: From 773ee6e7f6d40cf2de493c6fef5e3e493b497009 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 11 Feb 2026 21:27:53 +0530 Subject: [PATCH 2/3] FROMLIST: arm64: dts: qcom: talos: add ethernet node Add an ethernet controller node for QCS615 SoC to enable ethernet functionality. Link: https://lore.kernel.org/netdev/20250819-qcs615_eth-v4-3-5050ed3402cb@oss.qualcomm.com/ Signed-off-by: Yijie Yang Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/talos.dtsi | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index ca1f899a9c3fe..bcffaf1327f00 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -678,6 +678,40 @@ #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", + "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>; From 361fefe14011099f914ae71db232462e7b268a38 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 11 Feb 2026 21:30:18 +0530 Subject: [PATCH 3/3] FROMLIST: arm64: dts: qcom: qcs615-ride: Enable ethernet node Enable the ethernet node, add the phy node and pinctrl for ethernet. Link: https://lore.kernel.org/netdev/20250819-qcs615_eth-v4-4-5050ed3402cb@oss.qualcomm.com/ Signed-off-by: Yijie Yang Signed-off-by: Mohd Ayaan Anwar --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 102 +++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 851ff7de4d464..59ef546008539 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -372,6 +372,59 @@ }; }; +ðernet { + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + device_type = "ethernet-phy"; + reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + &gpu { status = "okay"; }; @@ -552,6 +605,55 @@ }; &tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + pps-pins { + pins = "gpio91"; + function = "rgmii"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio104"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + }; + bt_en_state: bt-en-state { pins = "gpio85"; function = "gpio";