From 56ba217546a6384774f1c7d00589e6074627fea0 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:15:32 +0530 Subject: [PATCH 01/21] Revert "dt-bindings: crypto: qcom,ice: Require power-domain and iface clk" This reverts commit 06997ee39f30680bea1e430c91093578f7c7a4e1. The revert for v1 patchset is required as it breaks the ABI compatability with existing device tree nodes and makes clock-names and power-domain as required properties. Signed-off-by: Abhinaba Rakshit --- .../bindings/crypto/qcom,inline-crypto-engine.yaml | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 1c2416117d4ce..c3408dcf5d205 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -28,20 +28,12 @@ properties: maxItems: 1 clocks: - maxItems: 2 - - clock-names: - maxItems: 2 - - power-domains: maxItems: 1 required: - compatible - reg - clocks - - clock-names - - power-domains additionalProperties: false @@ -53,10 +45,6 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; ... From 1d8ac48e7be8d92ce70058904a36c40f77db2ce5 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:25:49 +0530 Subject: [PATCH 02/21] Revert "arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node" This reverts commit a56ad585c68ba7917a473355d6325afce7936429. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index cd2c583f468bf..b4e918300c214 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2774,11 +2774,7 @@ compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From e01af7c17b84bc2a3dfe83c1b0b961d87455ba2d Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:26:58 +0530 Subject: [PATCH 03/21] Revert "arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node" This reverts commit 5eb6bf2a778e5ebe5ec8193b3ae3d967ca15e57c. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 600f145b26941..065aeab6d427e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2662,11 +2662,7 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; crypto: crypto@1dfa000 { From 0bdd61d1a113a1b1915ee0d361fcf7b5af53e259 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:27:54 +0530 Subject: [PATCH 04/21] Revert "arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node" This reverts commit ad4b5f429872acd550a36bfd4308304f333c756b. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 62af817475e7e..a0df10a97c7f8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1599,11 +1599,7 @@ compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; ipa: ipa@1e40000 { From 54067dc8c98d262599dc8f1cc4d0543fd08b52aa Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 27 Mar 2026 12:23:30 +0530 Subject: [PATCH 05/21] Revert "arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node" This reverts commit d28c004ae338c461f567496e8fdf517d753f6140. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7659b39719bf0..9f757221fcebc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2579,11 +2579,7 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From ab31b50f7a9cb76622209b4bd613395e1e8128a3 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:30:27 +0530 Subject: [PATCH 06/21] Revert "arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node" This reverts commit c7344f4e892d1b4e398c3e07cdb50089533f08d6. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6ea7917798b86..23420e6924728 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5349,11 +5349,7 @@ compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 201cba5c82bfe624d92a9e0667d4a356abc9c332 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:31:01 +0530 Subject: [PATCH 07/21] Revert "arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node" This reverts commit bf5281f90fa8cd15730031ed66f896575c7c934c. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9e7b8067edbb2..e294dc9c68c9a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2414,11 +2414,7 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; tcsr_mutex: hwlock@1f40000 { From 6fc243a7ceb11f0b2748dfb408c7811b315b8dc8 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:31:29 +0530 Subject: [PATCH 08/21] Revert "arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node" This reverts commit d061cc2ba97988c89378d30cd75c2193b0a80147. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 6e5d17eb31754..088604fa272c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4046,11 +4046,7 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 981e219689e3d96f29be8d44d6da6395381bf4cc Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:33:38 +0530 Subject: [PATCH 09/21] Revert "arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node" This reverts commit 646184aead7d98f472efde2cd546d8f790c25b48. Since, v1 patchset bindings change is reverted, corresponding devicetree changes also needs to be reverted. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 049afe2c72043..88805cb3f990a 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2058,11 +2058,7 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; - power-domains = <&gcc GCC_UFS_PHY_GDSC>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; cryptobam: dma-controller@1dc4000 { From 4f96f3cf40c2d129795eab2320ee2a59969c3aef Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 25 Mar 2026 00:34:39 +0530 Subject: [PATCH 10/21] Revert "soc: qcom: ice: Add explicit power-domain and clock voting calls for ICE" This reverts commit 7cb627041c5dc67c02d972c9c40093eabc7f770e. Revert v1 patchset driver changes as it breaks ABI compatability and does not work for ICE eMMC legacy bindings, which ends up causing device probe failures. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 4b50d05ca02a3..b203bc685cadd 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include @@ -110,7 +108,6 @@ struct qcom_ice { void __iomem *base; struct clk *core_clk; - struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -313,20 +310,12 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; - pm_runtime_get_sync(dev); err = clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; } - - err = clk_prepare_enable(ice->iface_clk); - if (err) { - dev_err(dev, "failed to enable iface clock (%d)\n", - err); - return err; - } qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } @@ -334,9 +323,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { - clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); - pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete = false; return 0; @@ -597,10 +584,6 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); - engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk"); - if (IS_ERR(engine->iface_clk)) - return ERR_CAST(engine->iface_clk); - if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -742,9 +725,6 @@ static int qcom_ice_probe(struct platform_device *pdev) return PTR_ERR(base); } - devm_pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - engine = qcom_ice_create(&pdev->dev, base); if (IS_ERR(engine)) return PTR_ERR(engine); From 27f1a48ef0fb769d0638f4163611aa7e1554a6f3 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 00:46:58 +0530 Subject: [PATCH 11/21] FROMLIST: dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.0) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-1-e36044bbdfe9@oss.qualcomm.com/ Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- .../crypto/qcom,inline-crypto-engine.yaml | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index c3408dcf5d205..9d5303a2557e0 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -28,6 +28,16 @@ properties: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: iface + + power-domains: maxItems: 1 required: @@ -37,6 +47,25 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-inline-crypto-engine + - qcom,milos-inline-crypto-engine + + then: + required: + - power-domains + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + examples: - | #include @@ -45,6 +74,10 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ... From 451e32af8f0ee57ec3e82586f61f79bea05e96b3 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:00:33 +0530 Subject: [PATCH 12/21] FROMLIST: soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-2-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver") Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd..bf4ab2d9e5c03 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -108,6 +108,7 @@ struct qcom_ice { void __iomem *base; struct clk *core_clk; + struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -312,8 +313,13 @@ int qcom_ice_resume(struct qcom_ice *ice) err = clk_prepare_enable(ice->core_clk); if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + dev_err(dev, "Failed to enable core clock: %d\n", err); + return err; + } + + err = clk_prepare_enable(ice->iface_clk); + if (err) { + dev_err(dev, "Failed to enable iface clock: %d\n", err); return err; } qcom_ice_hwkm_init(ice); @@ -323,6 +329,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { + clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); ice->hwkm_init_complete = false; @@ -579,11 +586,17 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); if (!engine->core_clk) engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "core"); if (!engine->core_clk) engine->core_clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); + engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface"); + if (IS_ERR(engine->iface_clk)) + return ERR_CAST(engine->iface_clk); + if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); From c3dbe732436aea320233b688f27ef8281e404a29 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:06:44 +0530 Subject: [PATCH 13/21] FROMLIST: arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-3-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index b385b46428834..12ee29fe64507 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -683,7 +683,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From eb0f0193edf26fa3bf7bca6fbd078afb47f8ba07 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:08:24 +0530 Subject: [PATCH 14/21] FROMLIST: arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-4-e36044bbdfe9@oss.qualcomm.com/ Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index b4e918300c214..e747cb7991f11 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2774,7 +2774,11 @@ compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 10b30b9ef03ee9a8b958edba76a31487f6d475eb Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:09:30 +0530 Subject: [PATCH 15/21] FROMLIST: arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-5-e36044bbdfe9@oss.qualcomm.com/ Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 065aeab6d427e..221904933a042 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2662,7 +2662,11 @@ compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; crypto: crypto@1dfa000 { From 6636e0f3d5cee4cf997823975d159c0d65c2ff68 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:10:51 +0530 Subject: [PATCH 16/21] FROMLIST: arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-6-e36044bbdfe9@oss.qualcomm.com/ Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a0df10a97c7f8..892b3d2f1bf99 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1599,7 +1599,11 @@ compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { From bf7100453f2b481854e493eebe9c6fab5f942cc1 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Fri, 27 Mar 2026 12:28:34 +0530 Subject: [PATCH 17/21] FROMLIST: arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-7-e36044bbdfe9@oss.qualcomm.com/ Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9f757221fcebc..708eb354d3b24 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2579,7 +2579,11 @@ compatible = "qcom,sc7280-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 5ad8ae478ec5a43d334ef4f4e38a3671249f3bd0 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:14:52 +0530 Subject: [PATCH 18/21] FROMLIST: arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-8-e36044bbdfe9@oss.qualcomm.com/ Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 23420e6924728..ba99bd34adb13 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5349,7 +5349,11 @@ compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From 782cd99c3bac620cdc62537c624f1b4cf7fdb49f Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:15:46 +0530 Subject: [PATCH 19/21] FROMLIST: arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-9-e36044bbdfe9@oss.qualcomm.com/ Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e294dc9c68c9a..7a56d2625014c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2414,7 +2414,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { From 9a0e391be9901c43d09c351cf35d662c1b60c0e5 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:17:12 +0530 Subject: [PATCH 20/21] FROMLIST: arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-10-e36044bbdfe9@oss.qualcomm.com/ Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 088604fa272c0..842396cf75d95 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4046,7 +4046,11 @@ "qcom,inline-crypto-engine"; reg = <0 0x01d88000 0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 { From d3326f55b10f6998fd923cef4221e8dc69e77805 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Wed, 25 Mar 2026 01:18:33 +0530 Subject: [PATCH 21/21] FROMLIST: arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-11-e36044bbdfe9@oss.qualcomm.com/ Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 88805cb3f990a..87cc7f6cbdf34 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2058,7 +2058,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; cryptobam: dma-controller@1dc4000 {