Contact Details
mseminario2@huskers.unl.edu
Request Details
I would like to update the Open RISC-V Implementations table - 'VestaRV' Description to the following, in order to be more concise:
RV32IMACZb* synthesizable mixed-signal MCU SoC for ASIC and FPGA
Contact Details
mseminario2@huskers.unl.edu
Request Details
I would like to update the Open RISC-V Implementations table - 'VestaRV' Description to the following, in order to be more concise:
RV32IMACZb* synthesizable mixed-signal MCU SoC for ASIC and FPGA