Mastering Interrupt Handling, ISR Design, and Exception Management
Learn to implement robust interrupt systems, design efficient ISRs, and handle exceptions for reliable embedded systems
- Overview
- Quick Reference: Key Facts
- Visual Understanding
- Conceptual Foundation
- Core Concepts
- Practical Considerations
- Additional Resources
Interrupts and exceptions are fundamental mechanisms that allow embedded systems to respond to external events and handle errors efficiently. Understanding interrupt handling is crucial for real-time system design and reliable embedded applications.
- Interrupt Vector Table: Maps interrupt sources to handler functions
- Interrupt Service Routine (ISR): Function executed when interrupt occurs
- Interrupt Latency: Time from interrupt occurrence to handler execution
- Exception Handling: Managing system errors and faults
- Priority Levels: ARM Cortex-M supports up to 256 priority levels
- Nesting: Higher priority interrupts can preempt lower priority ones
- Context Saving: CPU automatically saves/restores registers during ISR execution
- Can you design ISRs that are short, safe, and deterministic?
- Do you understand latency, priority, and nesting trade‑offs?
- Can you explain common fault/exception root causes?
Normal Execution → Interrupt Occurs → Context Save → ISR Execution → Context Restore → Resume Execution
↓ ↓ ↓ ↓ ↓ ↓
Main Loop Hardware Event Save Regs Process IRQ Restore Regs Continue
Priority 0 (Highest) ──┐
├── Can interrupt any lower priority
Priority 1 ────────────┤
├── Cannot interrupt Priority 0
Priority 2 ────────────┤
└── Cannot interrupt Priority 0 or 1
Priority 3 (Lowest) ───┘
Exceptions (Internal) Interrupts (External)
↓ ↓
Hardware Faults Peripheral Events
Memory Violations GPIO Changes
Illegal Instructions Timer Expiry
Stack Overflow Communication Events
Interrupts represent a fundamental shift from polling-based systems to event-driven architectures. Instead of continuously checking for events, the system waits for hardware to signal when something needs attention. This paradigm enables:
- Efficient Resource Usage: CPU sleeps until needed
- Real-Time Responsiveness: Immediate response to critical events
- Power Optimization: Reduced active time in battery-powered systems
Interrupts are the backbone of real-time embedded systems. They enable:
- Responsive User Interfaces: Immediate response to button presses
- Efficient Communication: Process data only when available
- System Reliability: Handle errors and faults gracefully
- Resource Management: Coordinate multiple hardware peripherals
Designing interrupt systems involves balancing several competing concerns:
- Latency vs. Complexity: Faster response requires simpler ISRs
- Priority vs. Fairness: Critical interrupts need immediate attention
- Safety vs. Performance: Robust error handling vs. minimal overhead
Why it matters: The vector table is the central nervous system of interrupt handling. It maps each interrupt source to its corresponding handler function, enabling the CPU to jump to the right code when interrupts occur.
Minimal example
// Basic interrupt handler registration
typedef void (*interrupt_handler_t)(void);
// Simple vector table structure
typedef struct {
interrupt_handler_t reset_handler;
interrupt_handler_t nmi_handler;
interrupt_handler_t hardfault_handler;
interrupt_handler_t irq_handlers[16]; // External interrupts
} vector_table_t;
// Register a handler for a specific interrupt
void register_interrupt_handler(uint8_t irq_number, interrupt_handler_t handler) {
if (irq_number < 16) {
vector_table.irq_handlers[irq_number] = handler;
}
}Try it: Create a simple vector table with handlers for timer and UART interrupts.
Takeaways
- Vector table must be properly aligned in memory
- Handler functions must have correct calling convention
- Unused interrupts should point to a default handler
Why it matters: ISR design directly impacts system responsiveness and reliability. Poorly designed ISRs can cause missed interrupts, priority inversion, and system instability.
Minimal example
// Good ISR design - minimal and fast
volatile bool data_ready = false;
volatile uint8_t received_data = 0;
void uart_rx_isr(void) {
// Clear interrupt flag immediately
UART1->SR &= ~UART_SR_RXNE;
// Minimal processing - just capture data
received_data = UART1->DR;
data_ready = true;
// Let main loop handle the data processing
}Try it: Design an ISR for a GPIO button press that sets a flag for main loop processing.
Takeaways
- Keep ISRs short and deterministic
- Avoid function calls and complex operations
- Use flags to communicate with main loop
- Clear interrupt flags early
Why it matters: Proper priority management ensures critical interrupts get immediate attention while preventing priority inversion and ensuring system responsiveness.
Minimal example
// Configure interrupt priorities
void configure_interrupt_priorities(void) {
// Set system timer to highest priority (lowest number)
NVIC_SetPriority(SysTick_IRQn, 0);
// Set UART to medium priority
NVIC_SetPriority(UART1_IRQn, 2);
// Set GPIO to lower priority
NVIC_SetPriority(EXTI0_IRQn, 4);
// Enable all interrupts
NVIC_EnableIRQ(SysTick_IRQn);
NVIC_EnableIRQ(UART1_IRQn);
NVIC_EnableIRQ(EXTI0_IRQn);
}Try it: Configure three interrupts with different priorities and observe nesting behavior.
Takeaways
- Lower priority numbers = higher priority
- Higher priority interrupts can preempt lower ones
- Consider system-wide priority strategy
- Test priority interactions thoroughly
Why it matters: Exceptions represent system errors that must be handled gracefully. Proper exception handling prevents system crashes and enables recovery from transient faults.
Minimal example
// Basic hard fault handler
void hardfault_handler(void) {
// Capture fault information
uint32_t fault_address = SCB->MMFAR; // Memory fault address
uint32_t fault_status = SCB->CFSR; // Combined fault status
// Log fault information (if possible)
log_fault_info(fault_address, fault_status);
// Attempt recovery or reset
if (can_recover_from_fault(fault_status)) {
// Try to continue
return;
} else {
// Reset system if recovery not possible
system_reset();
}
}Try it: Implement a fault handler that logs error information and attempts recovery.
Takeaways
- Always have exception handlers for critical faults
- Log fault information for debugging
- Implement recovery mechanisms when possible
- Reset system if recovery fails
Objective: Measure the time from interrupt trigger to ISR execution.
Steps:
- Configure a timer interrupt with known frequency
- Use GPIO toggles to mark interrupt entry/exit
- Measure timing with oscilloscope or logic analyzer
- Compare measured vs. theoretical latency
Expected Outcome: Understanding of interrupt overhead and factors affecting latency.
Objective: Observe how interrupt priorities affect nesting behavior.
Steps:
- Configure multiple interrupts with different priorities
- Trigger interrupts simultaneously
- Observe execution order and nesting
- Analyze priority inversion scenarios
Expected Outcome: Understanding of interrupt priority mechanisms and nesting behavior.
Objective: Implement robust exception handling for system faults.
Steps:
- Set up exception handlers for common faults
- Implement fault logging and recovery mechanisms
- Test fault scenarios (invalid memory access, divide by zero)
- Verify recovery behavior
Expected Outcome: Practical experience with exception handling and fault recovery.
- What is the difference between interrupts and exceptions?
- How does the interrupt vector table work?
- What are the key principles of ISR design?
- How would you design an interrupt-driven communication system?
- What factors affect interrupt latency?
- How do you handle interrupt priorities in a real-time system?
- How do you implement fault-tolerant exception handling?
- What are the trade-offs between interrupt-driven and polling-based systems?
- How do you debug interrupt-related issues?
- External Interrupts - Edge/level triggered interrupts, debouncing
- Watchdog Timers - System monitoring and recovery mechanisms
- Power Management - Sleep modes, wake-up sources, power consumption optimization
- Timer/Counter Programming - Input capture, output compare, frequency measurement
- Real_Time_Systems/Task_Creation_Management.md - Task scheduling and interrupt handling
- Embedded_C/Type_Qualifiers.md - Volatile usage in interrupt handlers
- Interrupt vs. Polling: Choose based on latency requirements and system load
- Priority Strategy: Define clear priority hierarchy based on system requirements
- ISR Complexity: Balance functionality with timing constraints
- Latency Minimization: Profile ISR execution time and optimize critical paths
- Memory Usage: Minimize stack usage in ISRs
- Cache Considerations: Ensure interrupt handlers are in cache-friendly memory
- Interrupt Debugging: Use GPIO toggles and logic analyzers for timing analysis
- Fault Injection: Test exception handling with controlled fault scenarios
- Performance Profiling: Measure interrupt frequency and execution time
- "Making Embedded Systems" by Elecia White
- "Programming Embedded Systems" by Michael Barr
- "Real-Time Systems" by Jane W. S. Liu
Next Topic: Reset Management → Timer/Counter Programming