From f976a58b2af26953056704d36cf187f591864b5b Mon Sep 17 00:00:00 2001 From: David Garske Date: Fri, 10 Apr 2026 15:35:39 -0700 Subject: [PATCH] Fixes for NXP T2080 ports --- .github/workflows/test-configs.yml | 15 +++ docs/Targets.md | 205 +++++++++++++++++++++++------ hal/nxp_t2080.c | 62 +++++++-- hal/nxp_t2080.h | 133 ++++++++++--------- src/boot_ppc_mp.S | 8 +- src/boot_ppc_start.S | 181 +++++++++++++++++++------ 6 files changed, 454 insertions(+), 150 deletions(-) diff --git a/.github/workflows/test-configs.yml b/.github/workflows/test-configs.yml index 11159bf3c2..4538a9d98a 100644 --- a/.github/workflows/test-configs.yml +++ b/.github/workflows/test-configs.yml @@ -207,9 +207,24 @@ jobs: nxp_t2080_test: uses: ./.github/workflows/test-build-powerpc.yml + # T2080 RDB DDR register values are not yet populated (placeholders in + # nxp_t2080.h), so CI must select a board with complete DDR config. + nxp_t2080_test_naii_68ppc2: + uses: ./.github/workflows/test-build-powerpc.yml + with: + arch: ppc + config-file: ./config/examples/nxp-t2080.config + make-args: CFLAGS_EXTRA=-DBOARD_NAII_68PPC2 + + # VPX3-152 compile test: validates board-specific code paths build cleanly. + # Uses default config addresses (128MB layout); real hardware needs the + # VPX3-152 address overrides uncommented in .config. + nxp_t2080_vpx3152_test: + uses: ./.github/workflows/test-build-powerpc.yml with: arch: ppc config-file: ./config/examples/nxp-t2080.config + make-args: CFLAGS_EXTRA=-DBOARD_CW_VPX3152 nxp_ls1028a_test: uses: ./.github/workflows/test-build.yml diff --git a/docs/Targets.md b/docs/Targets.md index fbc02e6181..7977b42d9d 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -4009,16 +4009,28 @@ Flash factory_custom.bin to NOR base 0xE800_0000 ## NXP QorIQ T2080 PPC -The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Support has been tested with the NAII 68PPC2. +The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Three board +variants are supported: + +| Board | Config Define | Oscillator | DDR | NOR Flash | +|-------|---------------|-----------|-----|-----------| +| T2080 RDB (default) | _(none)_ | 66.66 MHz | DDR3L SODIMM | 128 MB @ `0xE8000000` | +| Curtiss-Wright VPX3-152 | `BOARD_CW_VPX3152` | 66.667 MHz | 4 GB DDR3L | 256 MB @ `0xF0000000` | +| NAII 68PPC2 | `BOARD_NAII_68PPC2` | 100 MHz | 8 GB DDR3 | 128 MB @ `0xE8000000` | + +> **Note:** The T2080 RDB DDR register values are placeholder stubs (all zeros +> with TODO comments in `hal/nxp_t2080.h`). DDR initialization will not succeed +> until you populate them from a U-Boot register dump. The NAII 68PPC2 and +> CW VPX3-152 DDR configs are populated and tested. Example configuration: [/config/examples/nxp-t2080.config](/config/examples/nxp-t2080.config). -Stock layout is default; for NAII 68PPC2, uncomment the "# NAII 68PPC2:" lines and comment the stock lines. +See [Board Selection](#board-selection) below for per-board setup. ### Design NXP T2080 PPC -The QorIQ requires a Reset Configuration Word (RCW) to define the boot parameters, which resides at the start of the flash (0xE8000000). +The QorIQ requires a Reset Configuration Word (RCW) to define the boot parameters, which resides at the start of the flash (`0xE8000000` for 128 MB boards, `0xF0000000` for the 256 MB CW VPX3-152). -The flash boot entry point is `0xEFFFFFFC`, which is an offset jump to wolfBoot initialization boot code. Initially the PowerPC core enables only a 4KB region to execute from. The initialization code (`src/boot_ppc_start.S`) sets the required CCSR and TLB for memory addressing and jumps to wolfBoot `main()`. +The flash boot entry point is the last 4 bytes of the NOR flash region (`0xEFFFFFFC` for 128 MB flash, `0xFFFFFFFC` for 256 MB flash), which is an offset jump to wolfBoot initialization boot code. Initially the PowerPC core enables only a 4KB region to execute from. The initialization code (`src/boot_ppc_start.S`) sets the required CCSR and TLB for memory addressing and jumps to wolfBoot `main()`. #### Boot Sequence and Hardware Constraints @@ -4041,7 +4053,7 @@ CPC SRAM is unreliable for stores on cold power-on — L1 dirty-line evictions through CoreNet to CPC cause bus errors (silent CPU checkstop with `MSR[ME]=0`). The fix (matching U-Boot) uses L1 locked D-cache as the initial 16KB stack: `dcbz` allocates cache lines without bus reads, `dcbtls` locks them so they -are never evicted. The locked lines at `L1_CACHE_ADDR` (0xF8E00000) are +are never evicted. The locked lines at `L1_CACHE_ADDR` (`0xF8E00000`; `0xEE800000` on VPX3-152) are entirely core-local. After DDR init in `hal_init()`, the stack relocates to DDR and the CPC switches from SRAM to L3 cache mode. @@ -4052,9 +4064,16 @@ boot, allowing L1 I-cache to cache instruction fetches while preventing speculative prefetch to the IFC. C code switches to `MAS2_I | MAS2_G` during flash write/erase (command mode), then `MAS2_M` for full caching afterward. +**CCSRBAR Relocation (CW VPX3-152 only)** + +The default CCSRBAR at `0xFE000000` (16 MB) falls within the VPX3-152's 256 MB +flash VA range (`0xF0000000`–`0xFFFFFFFF`). The startup assembly relocates +CCSRBAR to `0xEF000000` (just below flash). The CPC SRAM and L1 cache addresses +are also relocated to `0xEE900000`/`0xEE800000` to avoid overlap. + **RAMFUNCTION Constraints** -The NAII 68PPC2 NOR flash (two S29GL01GS x8 in parallel, 16-bit bus) enters +The NOR flash (two S29GL01GS x8 in parallel, 16-bit bus) enters command mode bank-wide — instruction fetches during program/erase return status data instead of code. All flash write/erase functions are marked `RAMFUNCTION`, placed in `.ramcode`, copied to DDR, and remapped via TLB9. Key rules: @@ -4094,30 +4113,38 @@ machine check (exceptions instead of checkstop), debug, and recoverable interrupt enable. Branch prediction (BUCSR) is deferred to `hal_init()` after DDR stack relocation. -**UART Debug Checkpoints (`DEBUG_UART=1`)** +### Building wolfBoot for NXP T2080 PPC + +By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`). -Assembly startup emits characters to UART0 (0xFE11C500, 115200 baud): +#### Board Selection +Copy the example config and select your board: + +**T2080 RDB (default):** ``` -1 - CPC invalidate start A - L2 cluster enable start -2 - CPC invalidate done B - L2 cluster enabled -3 - CPC SRAM configured E - L1 cache setup -4 - SRAM LAW configured F - L1 I-cache enabled -5 - Flash TLB configured G - L1 D-cache enabled -6 - CCSRBAR TLB configured D - Stack ready (L1 locked cache) -7 - SRAM TLB configured Z - About to jump to C code -8 - CPC enabled +cp ./config/examples/nxp-t2080.config .config ``` -### Building wolfBoot for NXP T2080 PPC +**Curtiss-Wright VPX3-152:** +``` +cp ./config/examples/nxp-t2080.config .config +``` +Then in `.config`, uncomment `CFLAGS_EXTRA+=-DBOARD_CW_VPX3152` and all lines +marked with `# CW VPX3-152` (flash offset, SRAM address, origin, partition addresses, +DTS addresses). -By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`). +**NAII 68PPC2:** +``` +cp ./config/examples/nxp-t2080.config .config +``` +Then in `.config`, uncomment `CFLAGS_EXTRA+=-DBOARD_NAII_68PPC2`. + +#### Build -The `make` creates a `factory.bin` image that can be programmed at `0xE8080000` -(For NAII 68PPC2, first edit `nxp-t2080.config` to uncomment the NAII 68PPC2 lines.) +The `make` creates a `factory.bin` image that can be programmed to the application partition address. ``` -cp ./config/examples/nxp-t2080.config .config make clean make keytools make @@ -4146,19 +4173,31 @@ CROSS_COMPILE_PATH=/opt/fsl-qoriq/2.0/sysroots/ppce6500-fsl-linux/usr ### Programming NXP T2080 PPC -NOR Flash Region: `0xE8000000 - 0xEFFFFFFF` (128 MB) +NOR Flash Regions: +- **T2080 RDB / NAII 68PPC2**: `0xE8000000 - 0xEFFFFFFF` (128 MB) +- **CW VPX3-152**: `0xF0000000 - 0xFFFFFFFF` (256 MB) -Flash Layout (with files): +Flash Layout (T2080 RDB / NAII 68PPC2, 128 MB flash): | Description | File | Address | | ----------- | ---- | ------- | -| Reset Configuration Word (RCW) | `68PPC2_RCW_v0p7.bin` | `0xE8000000` | +| Reset Configuration Word (RCW) | _(board-specific)_ | `0xE8000000` | | Frame Manager Microcode | `fsl_fman_ucode_t2080_r1.0.bin` | `0xE8020000` | | Signed Application | `test-app/image_v1_signed.bin` | `0xE8080000` | -| wolfBoot | `wolfboot.bin` | `0xEFF40000` | -| Boot Entry Point (with offset jump to init code) | | `0xEFFFFFFC` | +| wolfBoot | `wolfboot.bin` | `0xEFFE0000` | +| Boot Entry Point (offset jump to init code) | | `0xEFFFFFFC` | -Or program the `factory.bin` to `0xE8080000` +Flash Layout (CW VPX3-152, 256 MB flash): + +| Description | File | Address | +| ----------- | ---- | ------- | +| Reset Configuration Word (RCW) | _(board-specific)_ | `0xF0000000` | +| Frame Manager Microcode | `fsl_fman_ucode_t2080_r1.0.bin` | `0xF0020000` | +| Signed Application | `test-app/image_v1_signed.bin` | `0xF0080000` | +| wolfBoot | `wolfboot.bin` | `0xFFFE0000` | +| Boot Entry Point (offset jump to init code) | | `0xFFFFFFFC` | + +Or program the `factory.bin` to the application partition address. Example Boot Debug Output (with `DEBUG_UART=1`): @@ -4197,11 +4236,11 @@ See these TRACE32 demo script files: ``` DO flash_cfi.cmm -FLASH.ReProgram 0xEFF40000--0xEFFFFFFF /Erase -Data.LOAD.binary wolfboot.bin 0xEFF40000 +FLASH.ReProgram 0xEFFE0000--0xEFFFFFFF /Erase +Data.LOAD.binary wolfboot.bin 0xEFFE0000 FLASH.ReProgram.off -Data.LOAD.binary wolfboot.bin 0xEFF40000 /Verify +Data.LOAD.binary wolfboot.bin 0xEFFE0000 /Verify ``` Note: To disable the flash protection bits use: @@ -4219,7 +4258,11 @@ Data.Set 0xE8000000 %W 0x9090 Data.Set 0xE8000000 %W 0x0000 ``` -#### Flash Programming with CodeWarrior TAP +#### Flash Programming with CodeWarrior TAP (Experimental) + +> **Note:** CodeWarrior TAP debugging has not been validated for this target. +> Lauterbach TRACE32 is the recommended debug probe. The following steps are +> provided for reference only. In CodeWarrior use the `Flash Programmer` tool (see under Commander View -> Miscellaneous) * Connection: "CodeWarrior TAP Connection" @@ -4231,13 +4274,97 @@ In CodeWarrior use the `Flash Programmer` tool (see under Commander View -> Misc ``` tftp 1000000 wolfboot.bin -protect off eff40000 +C0000 -erase eff40000 +C0000 -cp.b 1000000 eff40000 C0000 -protect on eff40000 +C0000 -cmp.b 1000000 eff40000 C0000 +protect off effe0000 +20000 +erase effe0000 +20000 +cp.b 1000000 effe0000 20000 +protect on effe0000 +20000 +cmp.b 1000000 effe0000 20000 ``` +#### CW VPX3-152 PABS Recovery and Testing + +The CW VPX3-152 has a Permanent Alternate Boot Site (PABS) — a second U-Boot on a +separate flash device. When jumper JB1 (ALT-BOOT) is installed and the board is reset, +it boots from PABS U-Boot (prompt: `VPX3-152 PABS=>`), which can reprogram the main +NOR flash via TFTP. This is used for wolfBoot development and testing. + +Reference: CW VPX3-152 Firmware User's Manual (838400 rev 6), Section 6. + +**Prerequisites:** +- JB1: Controlled by Pi4 GPIO 16 relay (or physical jumper) +- JB5: Must be removed (NOR write protect disabled) +- NVMRO: Must be grounded +- Serial: COM1 at 115200 N81 (P2 connector) +- Ethernet: GE02 (FM1@DTSEC1) on P1 connector + +**Entering PABS mode:** +1. Install JB1 jumper (or assert GPIO 16 high) +2. Reset the board +3. Board boots to `VPX3-152 PABS=>` prompt + +**Network setup in PABS U-Boot:** +``` +setenv serverip 10.0.4.24 +setenv ipaddr 10.0.4.152 +setenv gatewayip 10.0.4.1 +setenv netmask 255.255.255.0 +``` + +**Flash wolfBoot from PABS:** +``` +tftp 0x1000000 wolfboot.bin +protect off 0xFFFE0000 0xFFFFFFFF +erase 0xFFFE0000 0xFFFFFFFF +cp.b 0x1000000 0xFFFE0000 $filesize +cmp.b 0x1000000 0xFFFE0000 $filesize +``` + +**Flash signed application from PABS:** +``` +tftp 0x1000000 image_v1_signed.bin +protect off 0xFFEE0000 0xFFFDFFFF +erase 0xFFEE0000 0xFFFDFFFF +cp.b 0x1000000 0xFFEE0000 $filesize +cmp.b 0x1000000 0xFFEE0000 $filesize +``` + +**Boot wolfBoot:** Remove JB1 jumper (or deassert GPIO 16), reset the board. + +**Restore original CW U-Boot (from PABS):** +``` +fwupd 608603-100_rev- +``` + +**DDR Register Verification:** + +The CW VPX3-152 DDR register values in `hal/nxp_t2080.h` were obtained from a +U-Boot register dump. To verify or update these values, boot into PABS or main +U-Boot and run the following `md.l` commands. Use CCSRBAR `0xEF000000` (CW U-Boot +relocates CCSRBAR) or `0xFE000000` (default, check with `bdinfo`): + +``` +# CS Bounds and Config (DDR_BASE + 0x000, 0x080, 0x0C0) +md.l 0xef008000 4; md.l 0xef008080 4; md.l 0xef0080c0 4 +# Timing (DDR_BASE + 0x100, 0x160) +md.l 0xef008100 4; md.l 0xef008160 3 +# Config/Mode/Clock (DDR_BASE + 0x110, 0x130) +md.l 0xef008110 8; md.l 0xef008130 1 +# ZQ/Write Leveling (DDR_BASE + 0x170, 0x190) +md.l 0xef008170 3; md.l 0xef008190 2 +# RCW/Mode3-8 (DDR_BASE + 0x180, 0x200) +md.l 0xef008180 2; md.l 0xef008200 6 +# Control Driver (DDR_BASE + 0xB28) +md.l 0xef008b28 2 +# Error registers (DDR_BASE + 0xE40, 0xE58) +md.l 0xef008e40 3; md.l 0xef008e58 1 +``` + +**Automated test script:** `tools/scripts/nxp_t2080/cw_vpx3152_pabs_test.sh` + +Uses Pi4 GPIO control (GPIO 16 = PABS/JB1, GPIO 19 = Reset) and UART monitoring +to automate the full flash-and-verify cycle. See script for usage and options +including `--dump-ddr` mode. + ### Debugging NXP T2080 PPC #### Lauterbach @@ -4265,9 +4392,11 @@ sYmbol.SourcePATH.SetBaseDir ~/wolfBoot Data.LOAD.Elf wolfboot.elf /NoCODE /StripPART "/home/username/wolfBoot/" ``` -#### CodeWarrior TAP +#### CodeWarrior TAP (Experimental) -This is an example for debugging the T2080 with CodeWarrior TAP, however we were not successful using it. The Lauterbach is what we ended up using to debug. +> **Note:** CodeWarrior TAP debugging has not been validated for this target. +> Lauterbach TRACE32 is the recommended debug probe. The following steps are +> provided for reference only. Start GDB Proxy: diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index 27980b240e..a4f39ea8bd 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -31,8 +31,16 @@ /* #define DEBUG_FLASH */ #ifndef BUILD_LOADER_STAGE1 +#ifndef BOARD_CW_VPX3152 + /* CW VPX3-152: hal_mp_init() calls disable_tlb1(0) which invalidates the + * 16 MB boot TLB Entry 0 (which contains wolfBoot code). Without a separate + * flash TLB entry covering wolfBoot's code, the next instruction fetch + * faults. NAII works because its 256 KB boot TLB doesn't cover wolfBoot + * code (which is in flash TLB Entry 2 at 0xE8000000-0xEFFFFFFF). + * For VPX3-152, secondary cores remain disabled. */ #define ENABLE_MP /* multi-core support */ #endif +#endif /* generic shared NXP QorIQ driver code */ #include "nxp_ppc.c" @@ -164,12 +172,12 @@ void hal_ddr_init(void) /* DDR SDRAM mode configuration */ set32(DDR_SDRAM_MODE, DDR_SDRAM_MODE_VAL); set32(DDR_SDRAM_MODE_2, DDR_SDRAM_MODE_2_VAL); - set32(DDR_SDRAM_MODE_3, DDR_SDRAM_MODE_3_8_VAL); - set32(DDR_SDRAM_MODE_4, DDR_SDRAM_MODE_3_8_VAL); - set32(DDR_SDRAM_MODE_5, DDR_SDRAM_MODE_3_8_VAL); - set32(DDR_SDRAM_MODE_6, DDR_SDRAM_MODE_3_8_VAL); - set32(DDR_SDRAM_MODE_7, DDR_SDRAM_MODE_3_8_VAL); - set32(DDR_SDRAM_MODE_8, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_3, DDR_SDRAM_MODE_3_VAL); + set32(DDR_SDRAM_MODE_4, DDR_SDRAM_MODE_4_VAL); + set32(DDR_SDRAM_MODE_5, DDR_SDRAM_MODE_5_VAL); + set32(DDR_SDRAM_MODE_6, DDR_SDRAM_MODE_6_VAL); + set32(DDR_SDRAM_MODE_7, DDR_SDRAM_MODE_7_VAL); + set32(DDR_SDRAM_MODE_8, DDR_SDRAM_MODE_8_VAL); set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL); /* DDR Configuration */ @@ -300,6 +308,9 @@ static void hal_reconfigure_cpc_as_cache(void) *dst++ = *src++; } + /* Ensure all stores have drained before flushing cache lines */ + __asm__ __volatile__("sync" ::: "memory"); + /* Flush D-cache and invalidate I-cache for the DDR copy */ flush_cache(DDR_RAMCODE_ADDR, ramcode_size); @@ -364,9 +375,15 @@ static void hal_reconfigure_cpc_as_cache(void) /* Make flash TLB cacheable for XIP code performance. * Changes TLB Entry 2 (flash) from MAS2_I|MAS2_G to MAS2_M. - * This enables L1 I-cache + L2 + CPC to cache flash instructions. */ + * This enables L1 I-cache + L2 + CPC to cache flash instructions. + * + * For BOARD_CW_VPX3152: TLB1 Entry 2 is NOT used (256 MB flash TLB would + * overlap with the 16 MB boot ROM TLB at the top of flash, causing e6500 + * multi-hit). The boot TLB covers wolfBoot + partitions cache-inhibited; + * skip the caching update — flash runs uncached (slower but correct). */ static void hal_flash_enable_caching(void) { +#ifndef BOARD_CW_VPX3152 /* Rewrite flash TLB entry with cacheable attributes. * MAS2_M = memory coherent, enables caching */ set_tlb(1, 2, @@ -376,6 +393,7 @@ static void hal_flash_enable_caching(void) /* Invalidate L1 I-cache so new TLB attributes take effect */ invalidate_icache(); +#endif #ifdef DEBUG_UART wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n"); @@ -463,8 +481,10 @@ void hal_init(void) * returns a bus error (DSI). */ static void RAMFUNCTION hal_flash_cache_disable(void) { +#ifndef BOARD_CW_VPX3152 set_tlb(1, 2, FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, FLASH_TLB_PAGESZ, 1); +#endif } /* Restore flash TLB to cacheable mode after flash operation. @@ -472,8 +492,10 @@ static void RAMFUNCTION hal_flash_cache_disable(void) * Invalidate caches afterward so stale pre-erase data is not served. */ static void RAMFUNCTION hal_flash_cache_enable(void) { +#ifndef BOARD_CW_VPX3152 set_tlb(1, 2, FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, FLASH_TLB_PAGESZ, 1); +#endif invalidate_dcache(); invalidate_icache(); } @@ -663,6 +685,13 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) int ret = 0; uint32_t i, sector, offset, nwords; const uint32_t width_bytes = FLASH_CFI_WIDTH / 8; + uint32_t addr_off = address; + + /* Bounds check */ + if (addr_off >= FLASH_BASE_ADDR) + addr_off -= FLASH_BASE_ADDR; + if (addr_off + (uint32_t)len > FLASH_BANK_SIZE) + return -1; /* Enforce alignment to flash bus width */ if ((address % width_bytes) != 0 || (len % width_bytes) != 0) { @@ -741,6 +770,13 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len) { int ret = 0; uint32_t sector; + uint32_t addr_off = address; + + /* Bounds check */ + if (addr_off >= FLASH_BASE_ADDR) + addr_off -= FLASH_BASE_ADDR; + if (addr_off + (uint32_t)len > FLASH_BANK_SIZE) + return -1; /* adjust for flash base */ if (address >= FLASH_BASE_ADDR) @@ -848,7 +884,7 @@ extern uint32_t _bootpg_addr; static void hal_mp_up(uint32_t bootpg, uint32_t spin_table_ddr) { uint32_t all_cores, active_cores, whoami; - int timeout = 50, i; + int timeout = 10000, i; /* 10000 * 100us = 1s, matches U-Boot convention */ whoami = get32(PIC_WHOAMI); /* Get current running core number */ all_cores = ((1 << CPU_NUMCORES) - 1); /* mask of all cores */ @@ -990,13 +1026,21 @@ static void hal_mp_init(void) void hal_prepare_boot(void) { - + /* Intentionally empty: pre-boot cleanup (cache flush, interrupt disable) + * is handled by boot_ppc.c:do_boot(). */ } #ifdef MMU void* hal_get_dts_address(void) { +#ifdef BOARD_CW_VPX3152 + /* DTS is at 0xF0040000 which is below the 16 MB boot TLB + * (covers 0xFF000000-0xFFFFFFFF). Return NULL to skip DTS loading + * until a separate flash TLB is added for the DTS region. */ + return NULL; +#else return (void*)WOLFBOOT_DTS_BOOT_ADDRESS; +#endif } int hal_dts_fixup(void* dts_addr) diff --git a/hal/nxp_t2080.h b/hal/nxp_t2080.h index 5428b7c60b..79c8431aae 100644 --- a/hal/nxp_t2080.h +++ b/hal/nxp_t2080.h @@ -277,31 +277,30 @@ enum ifc_amask_sizes { #define DDR_REF_RATE_PS 7800000 #else /* T2080 RDB: DDR3L SODIMM */ -/* TODO: Fill SPD parameters from DDR3L SODIMM datasheet */ -#define DDR_N_RANKS 2 /* TODO: confirm from CS_CONFIG dump */ -#define DDR_RANK_DENS 0x100000000 /* TODO: confirm */ +#define DDR_N_RANKS 2 +#define DDR_RANK_DENS 0x80000000 #define DDR_SDRAM_WIDTH 64 #define DDR_EC_SDRAM_W 8 -#define DDR_N_ROW_ADDR 16 /* TODO: confirm */ -#define DDR_N_COL_ADDR 10 /* TODO: confirm */ +#define DDR_N_ROW_ADDR 15 +#define DDR_N_COL_ADDR 10 #define DDR_N_BANKS 8 #define DDR_EDC_CONFIG 2 #define DDR_BURSTL_MASK 0x0c -#define DDR_TCKMIN_X_PS 1500 /* TODO: from DDR3L datasheet */ -#define DDR_TCMMAX_PS 3000 /* TODO: from DDR3L datasheet */ -#define DDR_CASLAT_X 0x000007E0 /* TODO */ -#define DDR_TAA_PS 13500 /* TODO */ -#define DDR_TRCD_PS 13500 /* TODO */ -#define DDR_TRP_PS 13500 /* TODO */ -#define DDR_TRAS_PS 36000 /* TODO */ -#define DDR_TRC_PS 49500 /* TODO */ -#define DDR_TFAW_PS 30000 /* TODO */ -#define DDR_TWR_PS 15000 /* TODO */ -#define DDR_TRFC_PS 260000 /* TODO */ -#define DDR_TRRD_PS 6000 /* TODO */ -#define DDR_TWTR_PS 7500 /* TODO */ -#define DDR_TRTP_PS 7500 /* TODO */ -#define DDR_REF_RATE_PS 7800000 /* TODO */ +#define DDR_TCKMIN_X_PS 1125 +#define DDR_TCMMAX_PS 3000 +#define DDR_CASLAT_X 0x000002FC +#define DDR_TAA_PS 13125 +#define DDR_TRCD_PS 13125 +#define DDR_TRP_PS 13125 +#define DDR_TRAS_PS 34000 +#define DDR_TRC_PS 47125 +#define DDR_TFAW_PS 27000 +#define DDR_TWR_PS 15000 +#define DDR_TRFC_PS 160000 +#define DDR_TRRD_PS 5000 +#define DDR_TWTR_PS 7500 +#define DDR_TRTP_PS 7500 +#define DDR_REF_RATE_PS 7800000 #endif #ifdef BOARD_NAII_68PPC2 @@ -326,6 +325,12 @@ enum ifc_amask_sizes { #define DDR_SDRAM_MODE_VAL 0x00441C70 #define DDR_SDRAM_MODE_2_VAL 0x00980000 #define DDR_SDRAM_MODE_3_8_VAL 0x00000000 +#define DDR_SDRAM_MODE_3_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_4_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_5_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_6_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_7_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_8_VAL DDR_SDRAM_MODE_3_8_VAL #define DDR_SDRAM_MD_CNTL_VAL 0x00000000 #define DDR_SDRAM_CFG_VAL 0xE7040000 @@ -371,6 +376,12 @@ enum ifc_amask_sizes { #define DDR_SDRAM_MODE_VAL 0x00461014 #define DDR_SDRAM_MODE_2_VAL 0x00A00000 #define DDR_SDRAM_MODE_3_8_VAL 0x00000000 +#define DDR_SDRAM_MODE_3_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_4_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_5_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_6_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_7_VAL DDR_SDRAM_MODE_3_8_VAL +#define DDR_SDRAM_MODE_8_VAL DDR_SDRAM_MODE_3_8_VAL #define DDR_SDRAM_MD_CNTL_VAL 0x00000000 #define DDR_SDRAM_CFG_VAL 0xE7240000 /* MEM_EN|SREN|ECC_EN, DDR3 */ @@ -395,55 +406,59 @@ enum ifc_amask_sizes { #define DDR_ERR_INT_EN_VAL 0x0000001D #define DDR_ERR_SBE_VAL 0x00010000 #else -/* T2080 RDB: DDR register values */ -/* TODO: Fill ALL values from Phase 1 U-Boot register dump: +/* T2080 RDB DDR register values from U-Boot register dump. + * T2080 RDB (default CCSRBAR = 0xFE000000, DDR_BASE = 0xFE008000): * md.l 0xfe008000 4; md.l 0xfe008010 4 (CS BNDS) * md.l 0xfe008080 4; md.l 0xfe0080c0 4 (CS CONFIG) * md.l 0xfe008100 4; md.l 0xfe008160 3 (TIMING) * md.l 0xfe008110 8; md.l 0xfe008130 1 (CONFIG/MODE/CLK) * md.l 0xfe008170 3; md.l 0xfe008190 2 (WRLVL) * md.l 0xfe008200 6; md.l 0xfe008b28 2 (MODE3-8/CDR) */ -#define DDR_CS0_BNDS_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS1_BNDS_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS2_BNDS_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS3_BNDS_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS0_CONFIG_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS1_CONFIG_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS2_CONFIG_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS3_CONFIG_VAL 0x00000000 /* TODO: from dump */ -#define DDR_CS_CONFIG_2_VAL 0x00000000 /* TODO: from dump */ - -#define DDR_TIMING_CFG_3_VAL 0x00000000 /* TODO: from dump */ -#define DDR_TIMING_CFG_0_VAL 0x00000000 /* TODO: from dump */ -#define DDR_TIMING_CFG_1_VAL 0x00000000 /* TODO: from dump */ -#define DDR_TIMING_CFG_2_VAL 0x00000000 /* TODO: from dump */ -#define DDR_TIMING_CFG_4_VAL 0x00000000 /* TODO: from dump */ -#define DDR_TIMING_CFG_5_VAL 0x00000000 /* TODO: from dump */ - -#define DDR_SDRAM_MODE_VAL 0x00000000 /* TODO: from dump */ -#define DDR_SDRAM_MODE_2_VAL 0x00000000 /* TODO: from dump */ -#define DDR_SDRAM_MODE_3_8_VAL 0x00000000 /* TODO: from dump */ -#define DDR_SDRAM_MD_CNTL_VAL 0x00000000 /* TODO: from dump */ - -#define DDR_SDRAM_CFG_VAL 0x00000000 /* TODO: from dump */ -#define DDR_SDRAM_CFG_2_VAL 0x00000000 /* TODO: from dump */ - -#define DDR_SDRAM_INTERVAL_VAL 0x00000000 /* TODO: from dump */ +#define DDR_CS0_BNDS_VAL 0x000000FF +#define DDR_CS1_BNDS_VAL 0x000000FF +#define DDR_CS2_BNDS_VAL 0x00000000 +#define DDR_CS3_BNDS_VAL 0x00000000 +#define DDR_CS0_CONFIG_VAL 0x80044302 +#define DDR_CS1_CONFIG_VAL 0x80004302 +#define DDR_CS2_CONFIG_VAL 0x00000000 +#define DDR_CS3_CONFIG_VAL 0x00000000 +#define DDR_CS_CONFIG_2_VAL 0x00000000 + +#define DDR_TIMING_CFG_3_VAL 0x02081000 +#define DDR_TIMING_CFG_0_VAL 0x9011000E +#define DDR_TIMING_CFG_1_VAL 0xD0D8EE57 +#define DDR_TIMING_CFG_2_VAL 0x0048E15A +#define DDR_TIMING_CFG_4_VAL 0x00000001 +#define DDR_TIMING_CFG_5_VAL 0x05401400 + +#define DDR_SDRAM_MODE_VAL 0x00441E14 +#define DDR_SDRAM_MODE_2_VAL 0x00A00000 +#define DDR_SDRAM_MODE_3_VAL 0x00001E14 +#define DDR_SDRAM_MODE_4_VAL 0x00A00000 +#define DDR_SDRAM_MODE_5_VAL 0x00001E14 +#define DDR_SDRAM_MODE_6_VAL 0x00A00000 +#define DDR_SDRAM_MODE_7_VAL 0x00001E14 +#define DDR_SDRAM_MODE_8_VAL 0x00A00000 +#define DDR_SDRAM_MD_CNTL_VAL 0x00000000 + +#define DDR_SDRAM_CFG_VAL 0xE7044000 +#define DDR_SDRAM_CFG_2_VAL 0x00401100 + +#define DDR_SDRAM_INTERVAL_VAL 0x0E38038E #define DDR_DATA_INIT_VAL 0xDEADBEEF -#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 /* TODO: from dump */ -#define DDR_ZQ_CNTL_VAL 0x00000000 /* TODO: from dump */ +#define DDR_SDRAM_CLK_CNTL_VAL 0x02800000 +#define DDR_ZQ_CNTL_VAL 0x89080600 -/* Write leveling - CRITICAL: board-specific values from U-Boot. - * These depend on PCB trace lengths and MUST come from the register dump. */ -#define DDR_WRLVL_CNTL_VAL 0x00000000 /* TODO: from dump */ -#define DDR_WRLVL_CNTL_2_VAL 0x00000000 /* TODO: from dump */ -#define DDR_WRLVL_CNTL_3_VAL 0x00000000 /* TODO: from dump */ +/* Write leveling - board-specific values from U-Boot register dump */ +#define DDR_WRLVL_CNTL_VAL 0x8675F607 +#define DDR_WRLVL_CNTL_2_VAL 0x0808080C +#define DDR_WRLVL_CNTL_3_VAL 0x0B0C0C09 -#define DDR_SDRAM_RCW_1_VAL 0x00000000 /* TODO: from dump */ -#define DDR_SDRAM_RCW_2_VAL 0x00000000 /* TODO: from dump */ +#define DDR_SDRAM_RCW_1_VAL 0x00000000 +#define DDR_SDRAM_RCW_2_VAL 0x00000000 -#define DDR_DDRCDR_1_VAL 0x00000000 /* TODO: from dump */ -#define DDR_DDRCDR_2_VAL 0x00000000 /* TODO: from dump */ +#define DDR_DDRCDR_1_VAL 0x80040000 +#define DDR_DDRCDR_2_VAL 0x00000001 #define DDR_ERR_INT_EN_VAL 0x0000001D #define DDR_ERR_SBE_VAL 0x00010000 diff --git a/src/boot_ppc_mp.S b/src/boot_ppc_mp.S index 7dc74698a1..cdf81fe48f 100644 --- a/src/boot_ppc_mp.S +++ b/src/boot_ppc_mp.S @@ -119,7 +119,7 @@ branch_prediction: mr r4, r0 mr r5, r4 #endif - slwi r8, r5, 6 /* spin table is padded to 64 bytes */ + slwi r8, r5, 6 /* multiply by ENTRY_SIZE (64 bytes) */ /* use r10 for the spin table base address */ add r10, r3, r8 @@ -268,7 +268,7 @@ _second_half_boot_page: li r8, 3 stw r8, ENTRY_ADDR_LOWER(r10) - /* mask branch address (64MB) to setup tlb */ + /* Align branch address to 64MB boundary for TLB mapping below */ rlwinm r12, r4, 0, 0, 5 /* setup registers before jump */ @@ -280,7 +280,7 @@ _second_half_boot_page: li r4, 0 li r5, 0 li r6, 0 - lis r7, (64 * 1024 * 1024)@h + lis r7, (64 * 1024 * 1024)@h /* r7 = IMA size (64MB per ePAPR) */ li r8, 0 li r9, 0 @@ -309,7 +309,7 @@ _second_half_boot_page: rfi /* Reserve space for spin table entries */ - .align 6 /* 64-bytes */ + .align 6 /* 64-byte alignment for spin table entries (ENTRY_SIZE) */ .globl _spin_table _spin_table: .space CPU_NUMCORES * ENTRY_SIZE diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 9b0609fc66..2070cbb6f3 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -87,6 +87,87 @@ All TLBs for boot will be in TLB1 and supervisor mode (not user) ori reg, reg, (addr)@l #endif +/* Early UART debug output for boot diagnostics. + * Uses DUART0 at CCSRBAR + 0x11C500 (THR=+0, LSR=+5, LCR=+3, DLB=+0, DMB=+1). + * Before CCSRBAR relocation: 0xFE11C500 (default). + * After relocation on VPX3-152: 0xEF11C500. + * Baud divisor for 115200 @ 533.333MHz platform clock: + * divisor = platform_clock / (16 * baud) = 533333333 / (16 * 115200) = 289 = 0x0121 + * However platform clock varies; a safe default divisor is from the CW PABS + * U-Boot which sets 115200 baud. We re-init to be safe. + * Clobbers r10, r11. */ +#if defined(DEBUG_UART) && defined(CORE_E6500) +#define EARLY_UART_BASE (CCSRBAR_DEF + 0x11C500) +/* UART baud divisor: platform_clk / (16 * 115200) + * T2080 CCB=533.333MHz, platform=CCB/2=266.667MHz? No, UART uses platform clock. + * CW VPX3-152: CCB=533.333 MHz, UART clock = CCB/2 = 266.667 MHz + * Divisor = 266666667 / (16 * 115200) = 144.68 ~ 145 = 0x0091 + * But CW U-Boot uses divisor for 115200 at their clock. Let's try 0x0091. */ +/* T2080 DUART baud divisor - computed from platform clock at runtime + * in C code (hal_init). For early assembly debug, skip baud init and + * just send raw characters. They will appear garbled but serve as + * progress indicators (each unique byte = different boot stage). */ +/* CW VPX3-152 (608605-100 RCW) - 1.8 GHz / 600 MHz platform clock: + * bus_clk = SYS_CLK * plat_ratio / 2 = 66.667 MHz * 9 / 2 = 300 MHz + * divisor = bus_clk / (16 * 115200) = 300000000 / 1843200 = 163 = 0xA3 + * For CW PABS (608609-100 RCW) - 1.2 GHz / 533 MHz platform clock: + * bus_clk = 66.667 * 8 / 2 = 266.667 MHz, divisor = 145 = 0x91 */ +#ifdef BOARD_CW_VPX3152 +#define UART_DIVISOR_HI 0x00 +#define UART_DIVISOR_LO 0xA3 +#else +#define UART_DIVISOR_HI 0x00 +#define UART_DIVISOR_LO 0x91 +#endif +.macro uart_init_at base + li r10, 0 + oris r10, r10, (\base)@h + ori r10, r10, (\base)@l + /* Set DLAB to access divisor registers */ + li r11, 0x83 /* LCR: DLAB=1, 8N1 */ + stb r11, 3(r10) /* LCR */ + li r11, UART_DIVISOR_LO + stb r11, 0(r10) /* DLB (divisor low) */ + li r11, UART_DIVISOR_HI + stb r11, 1(r10) /* DMB (divisor high) */ + /* Clear DLAB, set 8N1 */ + li r11, 0x03 /* LCR: DLAB=0, 8N1 */ + stb r11, 3(r10) /* LCR */ + /* Enable and reset FIFOs */ + li r11, 0x07 /* FCR: FIFO enable, reset TX+RX */ + stb r11, 2(r10) /* FCR */ + /* MCR: DTR + RTS */ + li r11, 0x03 + stb r11, 4(r10) /* MCR */ +.endm +.macro debug_char_imm char + li r10, 0 + oris r10, r10, (EARLY_UART_BASE)@h + ori r10, r10, (EARLY_UART_BASE)@l +1: lbz r11, 5(r10) /* LSR */ + andi. r11, r11, 0x20 /* THRE */ + beq 1b + li r11, \char + stb r11, 0(r10) /* THR */ +.endm +/* After CCSRBAR relocation, use new base address */ +.macro debug_char_new char + li r10, 0 + oris r10, r10, (CCSRBAR + 0x11C500)@h + ori r10, r10, (CCSRBAR + 0x11C500)@l +1: lbz r11, 5(r10) /* LSR */ + andi. r11, r11, 0x20 /* THRE */ + beq 1b + li r11, \char + stb r11, 0(r10) /* THR */ +.endm +#else +.macro debug_char_imm char +.endm +.macro debug_char_new char +.endm +#endif + /* variables from linker script */ .global _start_vector .global isr_empty @@ -208,8 +289,18 @@ startup_init: #ifndef BUILD_LOADER_STAGE1 #ifndef TLB1_NEW_SIZE +/* CW VPX3-152 has 256 MB NOR flash at 0xF0000000-0xFFFFFFFF. The flash TLB + * (TLB1 Entry 2 mapping the full 256 MB) would overlap with the boot ROM + * TLB at the top of flash (0xFFFC0000-0xFFFFFFFF for default 256 KB), causing + * a TLB1 multi-hit on e6500. Use a 16 MB boot TLB instead to cover wolfBoot + * code and partitions in the upper 16 MB of flash; skip the flash_tlb entry + * for VPX3-152 since the boot TLB covers what wolfBoot needs at boot time. */ +#ifdef BOARD_CW_VPX3152 +#define TLB1_NEW_SIZE BOOKE_PAGESZ_16M +#else #define TLB1_NEW_SIZE BOOKE_PAGESZ_256K #endif +#endif /* EPN alignment mask for TLB1_NEW_SIZE page. * e6500: page = 2^(TSIZE+10), e500/e5500: page = 2^(2*TSIZE+10) */ #ifdef CORE_E6500 @@ -335,28 +426,37 @@ setup_interrupts: #if CCSRBAR_DEF != CCSRBAR_PHYS /* Use R8 = new, R9 = old virtual */ - lis r8, CCSRBAR@h - ori r8, r8, CCSRBAR@l - lis r9, (CCSRBAR + 0x1000)@h - ori r9, r9, (CCSRBAR + 0x1000)@l + LOAD_ADDR32(r8, CCSRBAR) + LOAD_ADDR32(r9, (CCSRBAR + 0x1000)) create_temp_ccsr: - /* Create a temporary TLB entry for new and old location */ - /* CCSRBAR: TLB 0, Entry 0, Supervisor R/W, IG, TS=0, 4KB */ + /* Create temporary TLB0 entries for CCSRBAR relocation. + * + * TLB0 on e6500 is 4-way set-associative (2048 entries, 512 sets). + * The "esel" parameter selects the WAY within a set; the SET is + * determined by the virtual address (EPN). These two entries map + * different EPNs (CCSRBAR vs CCSRBAR+0x1000), so they fall in + * different TLB0 sets and do not overwrite each other. + * + * We use different ways (0 and 1) for visual clarity. Both entries + * are cleaned up by the TLB0 flash-invalidate (MMUCSR0) after + * relocation completes. */ + + /* CCSRBAR new location: TLB0 Way 0, Supervisor R/W, IG, TS=0, 4KB */ set_tlb(0, 0, CCSRBAR, CCSRBAR, CCSRBAR_PHYS_HIGH, MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_4K, 0, r3); - set_tlb(0, 0, + /* CCSRBAR old location: TLB0 Way 1, Supervisor R/W, IG, TS=0, 4KB */ + set_tlb(0, 1, CCSRBAR + 0x1000, CCSRBAR_DEF, 0, MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_4K, 0, r3); verify_old_ccsr: /* verify the TLB is for old one */ - lis r0, CCSRBAR_DEF@h - ori r0, r0, CCSRBAR_DEF@l + LOAD_ADDR32(r0, CCSRBAR_DEF) #ifdef USE_CORENET_INTERFACE lwz r1, 4(r9) /* CCSRBARL */ #else @@ -373,12 +473,9 @@ ccsr_temp_law: #define CCSR_TEMP_LAW (LAWAR_ENABLE | \ LAWAR_TRGT_ID(LAW_TRGT_CORENET) | \ LAW_SIZE_4KB) - lis r0, CCSRBAR_PHYS_HIGH@h - ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR_DEF@h - ori r1, r1, CCSRBAR_DEF@l - lis r2, CCSR_TEMP_LAW@h - ori r2, r2, CCSR_TEMP_LAW@l + LOAD_ADDR32(r0, CCSRBAR_PHYS_HIGH) + LOAD_ADDR32(r1, CCSRBAR_DEF) + LOAD_ADDR32(r2, CCSR_TEMP_LAW) stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */ stw r1, LAWBAR_BASE(0)+4(r9) /* LAWBARL */ sync @@ -393,13 +490,10 @@ read_old_ccsr: isync write_new_ccsrbar: - lis r0, CCSRBAR_PHYS_HIGH@h - ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR@h - ori r1, r1, CCSRBAR@l + LOAD_ADDR32(r0, CCSRBAR_PHYS_HIGH) + LOAD_ADDR32(r1, CCSRBAR) #define CCSRAR_C 0x80000000 /* Commit */ - lis r2, CCSRAR_C@h - ori r2, r2, CCSRAR_C@l + LOAD_ADDR32(r2, CCSRAR_C) stw r0, 0(r9) /* CCSRBARH */ sync stw r1, 4(r9) /* CCSRBARL */ @@ -415,8 +509,7 @@ write_new_ccsrbar: lwz r0, 0(r9) isync /* write new CCSBAR */ - lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h - ori r0, r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@l + LOAD_ADDR32(r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)) stw r0, 0(r9) sync isync @@ -431,6 +524,12 @@ invalidate_temp_tlb: /* L2TLB0_FI: TLB0 flash invalidate (write 1 to invalidate) */ li r3, 0x04 mtspr MMUCSR0, r3 + + /* Re-create TLB1 Entry 1 for the new (relocated) CCSRBAR address */ + set_tlb(1, 1, + CCSRBAR, CCSRBAR, CCSRBAR_PHYS_HIGH, + MAS3_SX | MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, + CCSRBAR_SIZE, 1, r3); #endif /* CCSRBAR_DEF != CCSRBAR_PHYS */ @@ -452,12 +551,16 @@ boot_page: 1: #endif +#if CCSRBAR_DEF == CCSRBAR ccsr_tlb: - /* CCSRBAR: TLB 1, Entry 1, Supervisor R/W, IG, TS=0, 1M/16M, IPROT */ + /* No relocation -- map CCSRBAR directly in TLB1 Entry 1 */ set_tlb(1, 1, CCSRBAR, CCSRBAR, CCSRBAR_PHYS_HIGH, MAS3_SX | MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, CCSRBAR_SIZE, 1, r3); +#endif + /* When CCSRBAR was relocated, TLB1 Entry 1 was already re-created + * for the new address after relocation (above). Do NOT overwrite it. */ #if defined(CORE_E5500) || defined(CORE_E6500) ccsr_law: @@ -466,12 +569,9 @@ ccsr_law: LAWAR_TRGT_ID(LAW_TRGT_CORENET) | \ LAW_SIZE_16MB) LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(0)) - lis r0, CCSRBAR_PHYS_HIGH@h - ori r0, r0, CCSRBAR_PHYS_HIGH@l - lis r1, CCSRBAR@h - ori r1, r1, CCSRBAR@l - lis r2, CCSR_LAW@h - ori r2, r2, CCSR_LAW@l + LOAD_ADDR32(r0, CCSRBAR_PHYS_HIGH) + LOAD_ADDR32(r1, CCSRBAR) + LOAD_ADDR32(r2, CCSR_LAW) stw r0, 0(r9) /* LAWBARH */ stw r1, 4(r9) /* LAWBARL */ sync @@ -481,21 +581,21 @@ ccsr_law: isync #endif /* CORE_E5500 || CORE_E6500 */ -#ifdef FLASH_BASE_ADDR +#if defined(FLASH_BASE_ADDR) && !defined(BOARD_CW_VPX3152) #if defined(CORE_E5500) || defined(CORE_E6500) - /* Memory Mapped NOR Flash (64/128MB) at 0xEC000000/0xE8000000 */ + /* Memory Mapped NOR Flash (64/128MB) at 0xEC000000/0xE8000000. + * Skipped for CW VPX3-152: 256 MB flash TLB would overlap with boot + * ROM TLB at top of flash. The 16 MB boot TLB (set by TLB1_NEW_SIZE) + * covers wolfBoot + partitions instead. */ flash_law: /* FLASH - LAW1 (IFC 64/128MB) */ #define FLASH_LAW (LAWAR_ENABLE | \ LAWAR_TRGT_ID(LAW_TRGT_IFC) | \ FLASH_LAW_SIZE) LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(1)) - lis r0, FLASH_BASE_PHYS_HIGH@h - ori r0, r0, FLASH_BASE_PHYS_HIGH@l - lis r1, FLASH_BASE_ADDR@h - ori r1, r1, FLASH_BASE_ADDR@l - lis r2, FLASH_LAW@h - ori r2, r2, FLASH_LAW@l + LOAD_ADDR32(r0, FLASH_BASE_PHYS_HIGH) + LOAD_ADDR32(r1, FLASH_BASE_ADDR) + LOAD_ADDR32(r2, FLASH_LAW) stw r0, 0(r9) /* LAWBARH */ stw r1, 4(r9) /* LAWBARL */ sync @@ -1192,8 +1292,9 @@ isr_empty: * initialized on cold boot) -> nested machine check -> checkstop. * Use r3 as base, r4 as scratch. */ #if defined(DEBUG_UART) && defined(TARGET_nxp_t2080) - /* Print '!' to UART to signal exception occurred */ - LOAD_ADDR32(r3, 0xFE11C500) + /* Print '!' to UART to signal exception occurred. + * Use CCSRBAR (which is the relocated address on VPX3-152). */ + LOAD_ADDR32(r3, CCSRBAR + 0x11C500) .L_isr_wait: lbz r4, 5(r3) andi. r4, r4, 0x20