diff --git a/wolfcrypt/src/port/arm/armv8-32-curve25519.S b/wolfcrypt/src/port/arm/armv8-32-curve25519.S index 7c6765cf463..2e333d16387 100644 --- a/wolfcrypt/src/port/arm/armv8-32-curve25519.S +++ b/wolfcrypt/src/port/arm/armv8-32-curve25519.S @@ -2579,7 +2579,7 @@ fe_mul_op: adc r11, r11, #0 mov r12, #19 lsl r11, r11, #1 - orr r11, r11, r10, LSR #31 + orr r11, r11, r10, lsr #31 mul r11, r12, r11 ldm lr!, {r1, r2} mov r12, #38 @@ -3005,7 +3005,7 @@ fe_sq_op: adc r11, r11, #0 mov r12, #19 lsl r11, r11, #1 - orr r11, r11, r10, LSR #31 + orr r11, r11, r10, lsr #31 mul r11, r12, r11 ldm lr!, {r1, r2} mov r12, #38 @@ -3233,7 +3233,7 @@ fe_mul121666: mov r10, #19 adc lr, lr, #0 lsl lr, lr, #1 - orr lr, lr, r9, LSR #31 + orr lr, lr, r9, lsr #31 mul lr, r10, lr adds r2, r2, lr adcs r3, r3, #0 @@ -4375,7 +4375,7 @@ fe_sq2: adc r11, r11, #0 mov r12, #19 lsl r11, r11, #1 - orr r11, r11, r10, LSR #31 + orr r11, r11, r10, lsr #31 mul r11, r12, r11 ldm lr!, {r1, r2} mov r12, #38 @@ -4411,7 +4411,7 @@ fe_sq2: adds r8, r10, r11 # Reduce if top bit set mov r12, #19 - and r11, r12, r8, ASR #31 + and r11, r12, r8, asr #31 adds r1, r1, r11 adcs r2, r2, #0 adcs r3, r3, #0 @@ -4436,7 +4436,7 @@ fe_sq2: adc r8, r8, r8 # Reduce if top bit set mov r12, #19 - and r11, r12, r8, ASR #31 + and r11, r12, r8, asr #31 adds r1, r1, r11 adcs r2, r2, #0 adcs r3, r3, #0 @@ -4585,7 +4585,7 @@ fe_sq2: add r7, r7, lr # Reduce if top bit set mov r11, #19 - and r12, r11, r7, ASR #31 + and r12, r11, r7, asr #31 adds r0, r0, r12 adcs r1, r1, #0 adcs r2, r2, #0 @@ -4610,7 +4610,7 @@ fe_sq2: adc r7, r7, r7 # Reduce if top bit set mov r11, #19 - and r12, r11, r7, ASR #31 + and r12, r11, r7, asr #31 adds r0, r0, r12 adcs r1, r1, #0 adcs r2, r2, #0 @@ -5233,21 +5233,21 @@ sc_reduce: ldm r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9} lsr lr, r9, #24 lsl r9, r9, #4 - orr r9, r9, r8, LSR #28 + orr r9, r9, r8, lsr #28 lsl r8, r8, #4 - orr r8, r8, r7, LSR #28 + orr r8, r8, r7, lsr #28 lsl r7, r7, #4 - orr r7, r7, r6, LSR #28 + orr r7, r7, r6, lsr #28 lsl r6, r6, #4 - orr r6, r6, r5, LSR #28 + orr r6, r6, r5, lsr #28 lsl r5, r5, #4 - orr r5, r5, r4, LSR #28 + orr r5, r5, r4, lsr #28 lsl r4, r4, #4 - orr r4, r4, r3, LSR #28 + orr r4, r4, r3, lsr #28 lsl r3, r3, #4 - orr r3, r3, r2, LSR #28 + orr r3, r3, r2, lsr #28 lsl r2, r2, #4 - orr r2, r2, r1, LSR #28 + orr r2, r2, r1, lsr #28 #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) bic r9, r9, #0xf0000000 #else @@ -6018,21 +6018,21 @@ sc_reduce: ldm r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9} lsr lr, r9, #24 lsl r9, r9, #4 - orr r9, r9, r8, LSR #28 + orr r9, r9, r8, lsr #28 lsl r8, r8, #4 - orr r8, r8, r7, LSR #28 + orr r8, r8, r7, lsr #28 lsl r7, r7, #4 - orr r7, r7, r6, LSR #28 + orr r7, r7, r6, lsr #28 lsl r6, r6, #4 - orr r6, r6, r5, LSR #28 + orr r6, r6, r5, lsr #28 lsl r5, r5, #4 - orr r5, r5, r4, LSR #28 + orr r5, r5, r4, lsr #28 lsl r4, r4, #4 - orr r4, r4, r3, LSR #28 + orr r4, r4, r3, lsr #28 lsl r3, r3, #4 - orr r3, r3, r2, LSR #28 + orr r3, r3, r2, lsr #28 lsl r2, r2, #4 - orr r2, r2, r1, LSR #28 + orr r2, r2, r1, lsr #28 #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) bic r9, r9, #0xf0000000 #else @@ -7027,21 +7027,21 @@ sc_muladd: # Get 252..503 and 504..507 lsr lr, r9, #24 lsl r9, r9, #4 - orr r9, r9, r8, LSR #28 + orr r9, r9, r8, lsr #28 lsl r8, r8, #4 - orr r8, r8, r7, LSR #28 + orr r8, r8, r7, lsr #28 lsl r7, r7, #4 - orr r7, r7, r6, LSR #28 + orr r7, r7, r6, lsr #28 lsl r6, r6, #4 - orr r6, r6, r5, LSR #28 + orr r6, r6, r5, lsr #28 lsl r5, r5, #4 - orr r5, r5, r4, LSR #28 + orr r5, r5, r4, lsr #28 lsl r4, r4, #4 - orr r4, r4, r3, LSR #28 + orr r4, r4, r3, lsr #28 lsl r3, r3, #4 - orr r3, r3, r2, LSR #28 + orr r3, r3, r2, lsr #28 lsl r2, r2, #4 - orr r2, r2, r1, LSR #28 + orr r2, r2, r1, lsr #28 #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) bic r9, r9, #0xf0000000 #else @@ -7942,21 +7942,21 @@ sc_muladd: # Get 252..503 and 504..507 lsr lr, r9, #24 lsl r9, r9, #4 - orr r9, r9, r8, LSR #28 + orr r9, r9, r8, lsr #28 lsl r8, r8, #4 - orr r8, r8, r7, LSR #28 + orr r8, r8, r7, lsr #28 lsl r7, r7, #4 - orr r7, r7, r6, LSR #28 + orr r7, r7, r6, lsr #28 lsl r6, r6, #4 - orr r6, r6, r5, LSR #28 + orr r6, r6, r5, lsr #28 lsl r5, r5, #4 - orr r5, r5, r4, LSR #28 + orr r5, r5, r4, lsr #28 lsl r4, r4, #4 - orr r4, r4, r3, LSR #28 + orr r4, r4, r3, lsr #28 lsl r3, r3, #4 - orr r3, r3, r2, LSR #28 + orr r3, r3, r2, lsr #28 lsl r2, r2, #4 - orr r2, r2, r1, LSR #28 + orr r2, r2, r1, lsr #28 #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) bic r9, r9, #0xf0000000 #else diff --git a/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c b/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c index 1c6173814af..7ed31b978c2 100644 --- a/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c +++ b/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c @@ -2854,7 +2854,7 @@ WC_OMIT_FRAME_POINTER void fe_mul_op() "adc r11, r11, #0\n\t" "mov r12, #19\n\t" "lsl r11, r11, #1\n\t" - "orr r11, r11, r10, LSR #31\n\t" + "orr r11, r11, r10, lsr #31\n\t" "mul r11, r12, r11\n\t" "ldm lr!, {r1, r2}\n\t" "mov r12, #38\n\t" @@ -3323,7 +3323,7 @@ WC_OMIT_FRAME_POINTER void fe_sq_op() "adc r11, r11, #0\n\t" "mov r12, #19\n\t" "lsl r11, r11, #1\n\t" - "orr r11, r11, r10, LSR #31\n\t" + "orr r11, r11, r10, lsr #31\n\t" "mul r11, r12, r11\n\t" "ldm lr!, {r1, r2}\n\t" "mov r12, #38\n\t" @@ -3595,7 +3595,7 @@ WC_OMIT_FRAME_POINTER void fe_mul121666(fe r, fe a) "mov r10, #19\n\t" "adc lr, lr, #0\n\t" "lsl lr, lr, #1\n\t" - "orr lr, lr, r9, LSR #31\n\t" + "orr lr, lr, r9, lsr #31\n\t" "mul lr, r10, lr\n\t" "adds r2, r2, lr\n\t" "adcs r3, r3, #0\n\t" @@ -4850,7 +4850,7 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "adc r11, r11, #0\n\t" "mov r12, #19\n\t" "lsl r11, r11, #1\n\t" - "orr r11, r11, r10, LSR #31\n\t" + "orr r11, r11, r10, lsr #31\n\t" "mul r11, r12, r11\n\t" "ldm lr!, {r1, r2}\n\t" "mov r12, #38\n\t" @@ -4886,7 +4886,7 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "adds r8, r10, r11\n\t" /* Reduce if top bit set */ "mov r12, #19\n\t" - "and r11, r12, r8, ASR #31\n\t" + "and r11, r12, r8, asr #31\n\t" "adds r1, r1, r11\n\t" "adcs r2, r2, #0\n\t" "adcs r3, r3, #0\n\t" @@ -4911,7 +4911,7 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "adc r8, r8, r8\n\t" /* Reduce if top bit set */ "mov r12, #19\n\t" - "and r11, r12, r8, ASR #31\n\t" + "and r11, r12, r8, asr #31\n\t" "adds r1, r1, r11\n\t" "adcs r2, r2, #0\n\t" "adcs r3, r3, #0\n\t" @@ -5075,7 +5075,7 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "add r7, r7, lr\n\t" /* Reduce if top bit set */ "mov r11, #19\n\t" - "and r12, r11, r7, ASR #31\n\t" + "and r12, r11, r7, asr #31\n\t" "adds r0, r0, r12\n\t" "adcs r1, r1, #0\n\t" "adcs r2, r2, #0\n\t" @@ -5100,7 +5100,7 @@ WC_OMIT_FRAME_POINTER void fe_sq2(fe r, const fe a) "adc r7, r7, r7\n\t" /* Reduce if top bit set */ "mov r11, #19\n\t" - "and r12, r11, r7, ASR #31\n\t" + "and r12, r11, r7, asr #31\n\t" "adds r0, r0, r12\n\t" "adcs r1, r1, #0\n\t" "adcs r2, r2, #0\n\t" @@ -5885,21 +5885,21 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ldm %[s], {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "lsr lr, r9, #24\n\t" "lsl r9, r9, #4\n\t" - "orr r9, r9, r8, LSR #28\n\t" + "orr r9, r9, r8, lsr #28\n\t" "lsl r8, r8, #4\n\t" - "orr r8, r8, r7, LSR #28\n\t" + "orr r8, r8, r7, lsr #28\n\t" "lsl r7, r7, #4\n\t" - "orr r7, r7, r6, LSR #28\n\t" + "orr r7, r7, r6, lsr #28\n\t" "lsl r6, r6, #4\n\t" - "orr r6, r6, r5, LSR #28\n\t" + "orr r6, r6, r5, lsr #28\n\t" "lsl r5, r5, #4\n\t" - "orr r5, r5, r4, LSR #28\n\t" + "orr r5, r5, r4, lsr #28\n\t" "lsl r4, r4, #4\n\t" - "orr r4, r4, r3, LSR #28\n\t" + "orr r4, r4, r3, lsr #28\n\t" "lsl r3, r3, #4\n\t" - "orr r3, r3, r2, LSR #28\n\t" + "orr r3, r3, r2, lsr #28\n\t" "lsl r2, r2, #4\n\t" - "orr r2, r2, r1, LSR #28\n\t" + "orr r2, r2, r1, lsr #28\n\t" #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) "bic r9, r9, #0xf0000000\n\t" #else @@ -6685,21 +6685,21 @@ WC_OMIT_FRAME_POINTER void sc_reduce(byte* s) "ldm %[s], {r1, r2, r3, r4, r5, r6, r7, r8, r9}\n\t" "lsr lr, r9, #24\n\t" "lsl r9, r9, #4\n\t" - "orr r9, r9, r8, LSR #28\n\t" + "orr r9, r9, r8, lsr #28\n\t" "lsl r8, r8, #4\n\t" - "orr r8, r8, r7, LSR #28\n\t" + "orr r8, r8, r7, lsr #28\n\t" "lsl r7, r7, #4\n\t" - "orr r7, r7, r6, LSR #28\n\t" + "orr r7, r7, r6, lsr #28\n\t" "lsl r6, r6, #4\n\t" - "orr r6, r6, r5, LSR #28\n\t" + "orr r6, r6, r5, lsr #28\n\t" "lsl r5, r5, #4\n\t" - "orr r5, r5, r4, LSR #28\n\t" + "orr r5, r5, r4, lsr #28\n\t" "lsl r4, r4, #4\n\t" - "orr r4, r4, r3, LSR #28\n\t" + "orr r4, r4, r3, lsr #28\n\t" "lsl r3, r3, #4\n\t" - "orr r3, r3, r2, LSR #28\n\t" + "orr r3, r3, r2, lsr #28\n\t" "lsl r2, r2, #4\n\t" - "orr r2, r2, r1, LSR #28\n\t" + "orr r2, r2, r1, lsr #28\n\t" #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) "bic r9, r9, #0xf0000000\n\t" #else @@ -7714,21 +7714,21 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, /* Get 252..503 and 504..507 */ "lsr lr, r9, #24\n\t" "lsl r9, r9, #4\n\t" - "orr r9, r9, r8, LSR #28\n\t" + "orr r9, r9, r8, lsr #28\n\t" "lsl r8, r8, #4\n\t" - "orr r8, r8, r7, LSR #28\n\t" + "orr r8, r8, r7, lsr #28\n\t" "lsl r7, r7, #4\n\t" - "orr r7, r7, r6, LSR #28\n\t" + "orr r7, r7, r6, lsr #28\n\t" "lsl r6, r6, #4\n\t" - "orr r6, r6, r5, LSR #28\n\t" + "orr r6, r6, r5, lsr #28\n\t" "lsl r5, r5, #4\n\t" - "orr r5, r5, r4, LSR #28\n\t" + "orr r5, r5, r4, lsr #28\n\t" "lsl r4, r4, #4\n\t" - "orr r4, r4, %[c], LSR #28\n\t" + "orr r4, r4, %[c], lsr #28\n\t" "lsl %[c], %[c], #4\n\t" - "orr %[c], %[c], %[b], LSR #28\n\t" + "orr %[c], %[c], %[b], lsr #28\n\t" "lsl %[b], %[b], #4\n\t" - "orr %[b], %[b], %[a], LSR #28\n\t" + "orr %[b], %[b], %[a], lsr #28\n\t" #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) "bic r9, r9, #0xf0000000\n\t" #else @@ -8649,21 +8649,21 @@ WC_OMIT_FRAME_POINTER void sc_muladd(byte* s, const byte* a, const byte* b, /* Get 252..503 and 504..507 */ "lsr lr, r9, #24\n\t" "lsl r9, r9, #4\n\t" - "orr r9, r9, r8, LSR #28\n\t" + "orr r9, r9, r8, lsr #28\n\t" "lsl r8, r8, #4\n\t" - "orr r8, r8, r7, LSR #28\n\t" + "orr r8, r8, r7, lsr #28\n\t" "lsl r7, r7, #4\n\t" - "orr r7, r7, r6, LSR #28\n\t" + "orr r7, r7, r6, lsr #28\n\t" "lsl r6, r6, #4\n\t" - "orr r6, r6, r5, LSR #28\n\t" + "orr r6, r6, r5, lsr #28\n\t" "lsl r5, r5, #4\n\t" - "orr r5, r5, r4, LSR #28\n\t" + "orr r5, r5, r4, lsr #28\n\t" "lsl r4, r4, #4\n\t" - "orr r4, r4, %[c], LSR #28\n\t" + "orr r4, r4, %[c], lsr #28\n\t" "lsl %[c], %[c], #4\n\t" - "orr %[c], %[c], %[b], LSR #28\n\t" + "orr %[c], %[c], %[b], lsr #28\n\t" "lsl %[b], %[b], #4\n\t" - "orr %[b], %[b], %[a], LSR #28\n\t" + "orr %[b], %[b], %[a], lsr #28\n\t" #if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7) "bic r9, r9, #0xf0000000\n\t" #else diff --git a/wolfcrypt/src/port/arm/armv8-32-poly1305-asm.S b/wolfcrypt/src/port/arm/armv8-32-poly1305-asm.S index 2d91d0b6aa7..bcc3305e137 100644 --- a/wolfcrypt/src/port/arm/armv8-32-poly1305-asm.S +++ b/wolfcrypt/src/port/arm/armv8-32-poly1305-asm.S @@ -221,15 +221,15 @@ L_poly1305_arm32_16_loop: adds r4, r4, r3 lsr r3, r3, #2 adcs r5, r5, r9 - orr r3, r3, r9, LSL #30 + orr r3, r3, r9, lsl #30 adcs r6, r6, r10 lsr r9, r9, #2 adcs r7, r7, r11 - orr r9, r9, r10, LSL #30 + orr r9, r9, r10, lsl #30 adc r8, r8, r12 lsr r10, r10, #2 adds r4, r4, r3 - orr r10, r10, r11, LSL #30 + orr r10, r10, r11, lsl #30 adcs r5, r5, r9 lsr r11, r11, #2 adcs r6, r6, r10 @@ -535,15 +535,15 @@ L_poly1305_arm32_16_loop: adds r4, r4, r3 lsr r3, r3, #2 adcs r5, r5, r9 - orr r3, r3, r9, LSL #30 + orr r3, r3, r9, lsl #30 adcs r6, r6, r10 lsr r9, r9, #2 adcs r7, r7, r11 - orr r9, r9, r10, LSL #30 + orr r9, r9, r10, lsl #30 adc r8, r8, r12 lsr r10, r10, #2 adds r4, r4, r3 - orr r10, r10, r11, LSL #30 + orr r10, r10, r11, lsl #30 adcs r5, r5, r9 lsr r11, r11, #2 adcs r6, r6, r10 @@ -982,15 +982,15 @@ L_poly1305_arm32_blocks_start_1: adds r7, r7, r3 lsr r3, r3, #2 adcs r8, r8, r4 - orr r3, r3, r4, LSL #30 + orr r3, r3, r4, lsl #30 adcs r9, r9, r5 lsr r4, r4, #2 adcs r10, r10, r6 - orr r4, r4, r5, LSL #30 + orr r4, r4, r5, lsl #30 adc r11, r11, r12 lsr r5, r5, #2 adds r7, r7, r3 - orr r5, r5, r6, LSL #30 + orr r5, r5, r6, lsl #30 adcs r8, r8, r4 lsr r6, r6, #2 adcs r9, r9, r5 @@ -1127,15 +1127,15 @@ poly1305_set_key: adds r0, r0, r2 lsr r2, r2, #2 adcs r1, r1, r9 - orr r2, r2, r9, LSL #30 + orr r2, r2, r9, lsl #30 adcs r6, r6, r10 lsr r9, r9, #2 adcs r7, r7, r11 - orr r9, r9, r10, LSL #30 + orr r9, r9, r10, lsl #30 adc r8, r8, r12 lsr r10, r10, #2 adds r0, r0, r2 - orr r10, r10, r11, LSL #30 + orr r10, r10, r11, lsl #30 adcs r1, r1, r9 lsr r11, r11, #2 adcs r6, r6, r10 diff --git a/wolfcrypt/src/port/arm/armv8-32-poly1305-asm_c.c b/wolfcrypt/src/port/arm/armv8-32-poly1305-asm_c.c index 5d92ad44206..7a8a1e06111 100644 --- a/wolfcrypt/src/port/arm/armv8-32-poly1305-asm_c.c +++ b/wolfcrypt/src/port/arm/armv8-32-poly1305-asm_c.c @@ -253,15 +253,15 @@ WC_OMIT_FRAME_POINTER void poly1305_arm32_blocks_16(Poly1305* ctx, "adds r4, r4, %[notLast]\n\t" "lsr %[notLast], %[notLast], #2\n\t" "adcs r5, r5, r9\n\t" - "orr %[notLast], %[notLast], r9, LSL #30\n\t" + "orr %[notLast], %[notLast], r9, lsl #30\n\t" "adcs r6, r6, r10\n\t" "lsr r9, r9, #2\n\t" "adcs r7, r7, r11\n\t" - "orr r9, r9, r10, LSL #30\n\t" + "orr r9, r9, r10, lsl #30\n\t" "adc r8, r8, r12\n\t" "lsr r10, r10, #2\n\t" "adds r4, r4, %[notLast]\n\t" - "orr r10, r10, r11, LSL #30\n\t" + "orr r10, r10, r11, lsl #30\n\t" "adcs r5, r5, r9\n\t" "lsr r11, r11, #2\n\t" "adcs r6, r6, r10\n\t" @@ -624,15 +624,15 @@ WC_OMIT_FRAME_POINTER void poly1305_arm32_blocks_16(Poly1305* ctx, "adds r4, r4, %[notLast]\n\t" "lsr %[notLast], %[notLast], #2\n\t" "adcs r5, r5, r9\n\t" - "orr %[notLast], %[notLast], r9, LSL #30\n\t" + "orr %[notLast], %[notLast], r9, lsl #30\n\t" "adcs r6, r6, r10\n\t" "lsr r9, r9, #2\n\t" "adcs r7, r7, r11\n\t" - "orr r9, r9, r10, LSL #30\n\t" + "orr r9, r9, r10, lsl #30\n\t" "adc r8, r8, r12\n\t" "lsr r10, r10, #2\n\t" "adds r4, r4, %[notLast]\n\t" - "orr r10, r10, r11, LSL #30\n\t" + "orr r10, r10, r11, lsl #30\n\t" "adcs r5, r5, r9\n\t" "lsr r11, r11, #2\n\t" "adcs r6, r6, r10\n\t" @@ -1099,15 +1099,15 @@ WC_OMIT_FRAME_POINTER void poly1305_arm32_blocks(Poly1305* ctx, "adds r7, r7, r3\n\t" "lsr r3, r3, #2\n\t" "adcs r8, r8, r4\n\t" - "orr r3, r3, r4, LSL #30\n\t" + "orr r3, r3, r4, lsl #30\n\t" "adcs r9, r9, r5\n\t" "lsr r4, r4, #2\n\t" "adcs r10, r10, r6\n\t" - "orr r4, r4, r5, LSL #30\n\t" + "orr r4, r4, r5, lsl #30\n\t" "adc r11, r11, r12\n\t" "lsr r5, r5, #2\n\t" "adds r7, r7, r3\n\t" - "orr r5, r5, r6, LSL #30\n\t" + "orr r5, r5, r6, lsl #30\n\t" "adcs r8, r8, r4\n\t" "lsr r6, r6, #2\n\t" "adcs r9, r9, r5\n\t" @@ -1262,15 +1262,15 @@ WC_OMIT_FRAME_POINTER void poly1305_set_key(Poly1305* ctx, const byte* key) "adds %[ctx], %[ctx], r2\n\t" "lsr r2, r2, #2\n\t" "adcs %[key], %[key], r9\n\t" - "orr r2, r2, r9, LSL #30\n\t" + "orr r2, r2, r9, lsl #30\n\t" "adcs r6, r6, r10\n\t" "lsr r9, r9, #2\n\t" "adcs r7, r7, r11\n\t" - "orr r9, r9, r10, LSL #30\n\t" + "orr r9, r9, r10, lsl #30\n\t" "adc r8, r8, r12\n\t" "lsr r10, r10, #2\n\t" "adds %[ctx], %[ctx], r2\n\t" - "orr r10, r10, r11, LSL #30\n\t" + "orr r10, r10, r11, lsl #30\n\t" "adcs %[key], %[key], r9\n\t" "lsr r11, r11, #2\n\t" "adcs r6, r6, r10\n\t" diff --git a/wolfcrypt/src/port/riscv/riscv-64-aes.c b/wolfcrypt/src/port/riscv/riscv-64-aes.c index d81b1e1d188..fd1b516fe49 100644 --- a/wolfcrypt/src/port/riscv/riscv-64-aes.c +++ b/wolfcrypt/src/port/riscv/riscv-64-aes.c @@ -7443,8 +7443,8 @@ static int Aes128GcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz, "L_aes_gcm_128_decrypt_store_tag_byte:\n\t" "lb t2, (%[scratch])\n\t" "lb t3, (%[tag])\n\t" - "xor t0, t0, t2\n\t" - "xor t0, t0, t3\n\t" + "xor t3, t3, t2\n\t" + "or t0, t0, t3\n\t" "addi %[scratch], %[scratch], 1\n\t" "addi %[tag], %[tag], 1\n\t" "addi t1, t1, -1\n\t" @@ -7966,8 +7966,8 @@ static int Aes192GcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz, "L_aes_gcm_192_decrypt_store_tag_byte:\n\t" "lb t2, (%[scratch])\n\t" "lb t3, (%[tag])\n\t" - "xor t0, t0, t2\n\t" - "xor t0, t0, t3\n\t" + "xor t3, t3, t2\n\t" + "or t0, t0, t3\n\t" "addi %[scratch], %[scratch], 1\n\t" "addi %[tag], %[tag], 1\n\t" "addi t1, t1, -1\n\t" @@ -8506,8 +8506,8 @@ static int Aes256GcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz, "L_aes_gcm_256_decrypt_store_tag_byte:\n\t" "lb t2, (%[scratch])\n\t" "lb t3, (%[tag])\n\t" - "xor t0, t0, t2\n\t" - "xor t0, t0, t3\n\t" + "xor t3, t3, t2\n\t" + "or t0, t0, t3\n\t" "addi %[scratch], %[scratch], 1\n\t" "addi %[tag], %[tag], 1\n\t" "addi t1, t1, -1\n\t" diff --git a/wolfcrypt/src/sp_arm32.c b/wolfcrypt/src/sp_arm32.c index 62a7376a53a..dd05a2578f2 100644 --- a/wolfcrypt/src/sp_arm32.c +++ b/wolfcrypt/src/sp_arm32.c @@ -91902,7 +91902,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_add_12(sp_digit* r, "sbcs r11, r11, r3\n\t" "stm %[r]!, {r8, r9, r10, r11}\n\t" "ldm %[r], {r8, r9, r10, r11}\n\t" - "sbcs r8, r8, r12, LSL #1\n\t" + "sbcs r8, r8, r12, lsl #1\n\t" "sbcs r9, r9, r3\n\t" "sbcs r10, r10, r3\n\t" "sbcs r11, r11, r3\n\t" @@ -91924,7 +91924,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_add_12(sp_digit* r, "sbcs r11, r11, r3\n\t" "stm %[r]!, {r8, r9, r10, r11}\n\t" "ldm %[r], {r8, r9, r10, r11}\n\t" - "sbcs r8, r8, r12, LSL #1\n\t" + "sbcs r8, r8, r12, lsl #1\n\t" "sbcs r9, r9, r3\n\t" "sbcs r10, r10, r3\n\t" "sbcs r11, r11, r3\n\t" @@ -91994,7 +91994,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_dbl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92014,7 +92014,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_dbl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92083,7 +92083,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_tpl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92103,7 +92103,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_tpl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92147,7 +92147,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_tpl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92167,7 +92167,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_tpl_12(sp_digit* r, "sbcs r5, r5, #0\n\t" "sbcs r6, r6, #0\n\t" "sbcs r7, r7, r2\n\t" - "sbcs r8, r8, r3, LSL #1\n\t" + "sbcs r8, r8, r3, lsl #1\n\t" "sbcs r9, r9, r2\n\t" "stm %[r]!, {r4, r5, r6, r7, r8, r9}\n\t" "ldm %[r], {r4, r5, r6, r7, r8, r9}\n\t" @@ -92437,7 +92437,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_sub_12(sp_digit* r, "adcs r11, r11, r3\n\t" "stm %[r]!, {r8, r9, r10, r11}\n\t" "ldm %[r], {r8, r9, r10, r11}\n\t" - "adcs r8, r8, r12, LSL #1\n\t" + "adcs r8, r8, r12, lsl #1\n\t" "adcs r9, r9, r3\n\t" "adcs r10, r10, r3\n\t" "adcs r11, r11, r3\n\t" @@ -92458,7 +92458,7 @@ WC_OMIT_FRAME_POINTER static void sp_384_mont_sub_12(sp_digit* r, "adcs r11, r11, r3\n\t" "stm %[r]!, {r8, r9, r10, r11}\n\t" "ldm %[r], {r8, r9, r10, r11}\n\t" - "adcs r8, r8, r12, LSL #1\n\t" + "adcs r8, r8, r12, lsl #1\n\t" "adcs r9, r9, r3\n\t" "adcs r10, r10, r3\n\t" "adcs r11, r11, r3\n\t" diff --git a/wolfcrypt/src/sp_cortexm.c b/wolfcrypt/src/sp_cortexm.c index a36602d1952..08b3b31a659 100644 --- a/wolfcrypt/src/sp_cortexm.c +++ b/wolfcrypt/src/sp_cortexm.c @@ -40752,10 +40752,10 @@ WC_OMIT_FRAME_POINTER static void sp_256_rshift1_8(sp_digit* r, "LSR r7, r3, #1\n\t" "LSR r8, r4, #1\n\t" "LSR r9, r5, #1\n\t" - "ORR r6, r6, r3, lsl #31\n\t" - "ORR r7, r7, r4, lsl #31\n\t" - "ORR r8, r8, r5, lsl #31\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r6, r6, r3, LSL #31\n\t" + "ORR r7, r7, r4, LSL #31\n\t" + "ORR r8, r8, r5, LSL #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "MOV r10, r2\n\t" "STRD r6, r7, [%[r], #16]\n\t" "STRD r8, r9, [%[r], #24]\n\t" @@ -40765,10 +40765,10 @@ WC_OMIT_FRAME_POINTER static void sp_256_rshift1_8(sp_digit* r, "LSR r7, r3, #1\n\t" "LSR r8, r4, #1\n\t" "LSR r9, r5, #1\n\t" - "ORR r6, r6, r3, lsl #31\n\t" - "ORR r7, r7, r4, lsl #31\n\t" - "ORR r8, r8, r5, lsl #31\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r6, r6, r3, LSL #31\n\t" + "ORR r7, r7, r4, LSL #31\n\t" + "ORR r8, r8, r5, LSL #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "STRD r6, r7, [%[r]]\n\t" "STRD r8, r9, [%[r], #8]\n\t" : [r] "+r" (r), [a] "+r" (a) @@ -40849,10 +40849,10 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, "LSR r9, r5, #1\n\t" "LSR r10, r6, #1\n\t" "LSR r11, r7, #1\n\t" - "ORR r8, r8, r5, lsl #31\n\t" - "ORR r9, r9, r6, lsl #31\n\t" - "ORR r10, r10, r7, lsl #31\n\t" - "ORR r11, r11, r3, lsl #31\n\t" + "ORR r8, r8, r5, LSL #31\n\t" + "ORR r9, r9, r6, LSL #31\n\t" + "ORR r10, r10, r7, LSL #31\n\t" + "ORR r11, r11, r3, LSL #31\n\t" "MOV r3, r4\n\t" "STRD r8, r9, [%[r], #16]\n\t" "STRD r10, r11, [%[r], #24]\n\t" @@ -40861,10 +40861,10 @@ WC_OMIT_FRAME_POINTER static void sp_256_div2_mod_8(sp_digit* r, "LSR r9, r5, #1\n\t" "LSR r10, r6, #1\n\t" "LSR r11, r7, #1\n\t" - "ORR r8, r8, r5, lsl #31\n\t" - "ORR r9, r9, r6, lsl #31\n\t" - "ORR r10, r10, r7, lsl #31\n\t" - "ORR r11, r11, r3, lsl #31\n\t" + "ORR r8, r8, r5, LSL #31\n\t" + "ORR r9, r9, r6, LSL #31\n\t" + "ORR r10, r10, r7, LSL #31\n\t" + "ORR r11, r11, r3, LSL #31\n\t" "STM %[r], {r8, r9, r10, r11}\n\t" : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) : @@ -45811,47 +45811,47 @@ WC_OMIT_FRAME_POINTER static void sp_384_rshift1_12(sp_digit* r, __asm__ __volatile__ ( "LDM %[a], {r2, r3}\n\t" "LSR r2, r2, #1\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #8]\n\t" "STR r2, [%[r]]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #12]\n\t" "STR r3, [%[r], #4]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #16]\n\t" "STR r4, [%[r], #8]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #20]\n\t" "STR r2, [%[r], #12]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #24]\n\t" "STR r3, [%[r], #16]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #28]\n\t" "STR r4, [%[r], #20]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #32]\n\t" "STR r2, [%[r], #24]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #36]\n\t" "STR r3, [%[r], #28]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #40]\n\t" "STR r4, [%[r], #32]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #44]\n\t" "STR r2, [%[r], #36]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "STR r3, [%[r], #40]\n\t" "STR r4, [%[r], #44]\n\t" @@ -50684,49 +50684,49 @@ WC_OMIT_FRAME_POINTER static void sp_384_div2_mod_12(sp_digit* r, "SUB %[r], %[r], #0x30\n\t" "LDRD r8, r9, [%[r]]\n\t" "LSR r8, r8, #1\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #8]\n\t" "STR r8, [%[r]]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #12]\n\t" "STR r9, [%[r], #4]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #16]\n\t" "STR r10, [%[r], #8]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #20]\n\t" "STR r8, [%[r], #12]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #24]\n\t" "STR r9, [%[r], #16]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #28]\n\t" "STR r10, [%[r], #20]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #32]\n\t" "STR r8, [%[r], #24]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #36]\n\t" "STR r9, [%[r], #28]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #40]\n\t" "STR r10, [%[r], #32]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #44]\n\t" "STR r8, [%[r], #36]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" - "ORR r10, r10, r3, lsl #31\n\t" + "ORR r10, r10, r3, LSL #31\n\t" "STR r9, [%[r], #40]\n\t" "STR r10, [%[r], #44]\n\t" : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) @@ -57590,67 +57590,67 @@ WC_OMIT_FRAME_POINTER static void sp_521_rshift1_17(sp_digit* r, __asm__ __volatile__ ( "LDM %[a], {r2, r3}\n\t" "LSR r2, r2, #1\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #8]\n\t" "STR r2, [%[r]]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #12]\n\t" "STR r3, [%[r], #4]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #16]\n\t" "STR r4, [%[r], #8]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #20]\n\t" "STR r2, [%[r], #12]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #24]\n\t" "STR r3, [%[r], #16]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #28]\n\t" "STR r4, [%[r], #20]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #32]\n\t" "STR r2, [%[r], #24]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #36]\n\t" "STR r3, [%[r], #28]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #40]\n\t" "STR r4, [%[r], #32]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #44]\n\t" "STR r2, [%[r], #36]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #48]\n\t" "STR r3, [%[r], #40]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #52]\n\t" "STR r4, [%[r], #44]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #56]\n\t" "STR r2, [%[r], #48]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #60]\n\t" "STR r3, [%[r], #52]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #64]\n\t" "STR r4, [%[r], #56]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "STR r2, [%[r], #60]\n\t" "STR r3, [%[r], #64]\n\t" @@ -63790,69 +63790,69 @@ WC_OMIT_FRAME_POINTER static void sp_521_div2_mod_17(sp_digit* r, "SUB %[r], %[r], #0x44\n\t" "LDRD r8, r9, [%[r]]\n\t" "LSR r8, r8, #1\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #8]\n\t" "STR r8, [%[r]]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #12]\n\t" "STR r9, [%[r], #4]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #16]\n\t" "STR r10, [%[r], #8]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #20]\n\t" "STR r8, [%[r], #12]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #24]\n\t" "STR r9, [%[r], #16]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #28]\n\t" "STR r10, [%[r], #20]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #32]\n\t" "STR r8, [%[r], #24]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #36]\n\t" "STR r9, [%[r], #28]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #40]\n\t" "STR r10, [%[r], #32]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #44]\n\t" "STR r8, [%[r], #36]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #48]\n\t" "STR r9, [%[r], #40]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #52]\n\t" "STR r10, [%[r], #44]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" "LDR r10, [%[r], #56]\n\t" "STR r8, [%[r], #48]\n\t" - "ORR r9, r9, r10, lsl #31\n\t" + "ORR r9, r9, r10, LSL #31\n\t" "LSR r10, r10, #1\n\t" "LDR r8, [%[r], #60]\n\t" "STR r9, [%[r], #52]\n\t" - "ORR r10, r10, r8, lsl #31\n\t" + "ORR r10, r10, r8, LSL #31\n\t" "LSR r8, r8, #1\n\t" "LDR r9, [%[r], #64]\n\t" "STR r10, [%[r], #56]\n\t" - "ORR r8, r8, r9, lsl #31\n\t" + "ORR r8, r8, r9, LSL #31\n\t" "LSR r9, r9, #1\n\t" - "ORR r9, r9, r3, lsl #31\n\t" + "ORR r9, r9, r3, LSL #31\n\t" "STR r8, [%[r], #60]\n\t" "STR r9, [%[r], #64]\n\t" : [r] "+r" (r), [a] "+r" (a), [m] "+r" (m) @@ -72076,127 +72076,127 @@ WC_OMIT_FRAME_POINTER static void sp_1024_rshift1_32(sp_digit* r, __asm__ __volatile__ ( "LDM %[a], {r2, r3}\n\t" "LSR r2, r2, #1\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #8]\n\t" "STR r2, [%[r]]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #12]\n\t" "STR r3, [%[r], #4]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #16]\n\t" "STR r4, [%[r], #8]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #20]\n\t" "STR r2, [%[r], #12]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #24]\n\t" "STR r3, [%[r], #16]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #28]\n\t" "STR r4, [%[r], #20]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #32]\n\t" "STR r2, [%[r], #24]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #36]\n\t" "STR r3, [%[r], #28]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #40]\n\t" "STR r4, [%[r], #32]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #44]\n\t" "STR r2, [%[r], #36]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #48]\n\t" "STR r3, [%[r], #40]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #52]\n\t" "STR r4, [%[r], #44]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #56]\n\t" "STR r2, [%[r], #48]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #60]\n\t" "STR r3, [%[r], #52]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #64]\n\t" "STR r4, [%[r], #56]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #68]\n\t" "STR r2, [%[r], #60]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #72]\n\t" "STR r3, [%[r], #64]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #76]\n\t" "STR r4, [%[r], #68]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #80]\n\t" "STR r2, [%[r], #72]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #84]\n\t" "STR r3, [%[r], #76]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #88]\n\t" "STR r4, [%[r], #80]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #92]\n\t" "STR r2, [%[r], #84]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #96]\n\t" "STR r3, [%[r], #88]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #100]\n\t" "STR r4, [%[r], #92]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #104]\n\t" "STR r2, [%[r], #96]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #108]\n\t" "STR r3, [%[r], #100]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #112]\n\t" "STR r4, [%[r], #104]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "LDR r4, [%[a], #116]\n\t" "STR r2, [%[r], #108]\n\t" - "ORR r3, r3, r4, lsl #31\n\t" + "ORR r3, r3, r4, LSL #31\n\t" "LSR r4, r4, #1\n\t" "LDR r2, [%[a], #120]\n\t" "STR r3, [%[r], #112]\n\t" - "ORR r4, r4, r2, lsl #31\n\t" + "ORR r4, r4, r2, LSL #31\n\t" "LSR r2, r2, #1\n\t" "LDR r3, [%[a], #124]\n\t" "STR r4, [%[r], #116]\n\t" - "ORR r2, r2, r3, lsl #31\n\t" + "ORR r2, r2, r3, LSL #31\n\t" "LSR r3, r3, #1\n\t" "STR r2, [%[r], #120]\n\t" "STR r3, [%[r], #124]\n\t"