"I don't just write code; I design a complete embedded product with a full process from requirement analysis, schematic design & PCB to software architecture development."
I am currently a Computer Engineering student at VNUHCM-UIT (GPA: 8.55/10). My passion is mastering the entire process and complex engineering steps to perfect products and solve real-world problems.
- 🔭 Current Focus: Developing bare-metal drivers for STM32, multi-core RTOS systems on ESP32; Designing custom schematics & PCBs for STM32 & ESP32 projects.
- 🌱 Core Philosophy: Deep understanding of core process & underlaying logic designs.
- 🗣️ Languages: Vietnamese (Native), English (C1 - Proficient).
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Challenges: Bare-metal Optimization (64KB Flash), Class 0.5S Accuracy (IEC 62053-22), 3-Phase Industrial Simulation, Fail-safe Robustness.
- Architect a professional-grade firmware using a Bare-metal approach to maximize performance within a constrained 64KB Flash/20KB RAM footprint, avoiding the overhead of HAL libraries.
- Develop a dual-update strategy: A custom bootloader supporting XMODEM-CRC via UART for remote servicing and a microSD-based recovery mechanism for offline field maintenance.
- Engineer a high-reliability system with a multi-layered safety net: IWDG (LSI-based) for hardware hangs, WWDG for software logic faults, and CSS (Clock Security System) to monitor HSE oscillator stability.
- Implement precise energy metering logic using ADE7758, achieving Class 0.5S accuracy for parameters including Vrms, Irms, Active/Reactive Power, and Power Factor across 3 phases.
- Design a Hardware-in-the-Loop (HIL) testbench using MCP4728 (DAC) and TDA2030 amplifiers to simulate industrial 3-phase signals from a single-phase source, enabling comprehensive validation without high-voltage risks.
- Integrate advanced security and power features: Using Backup Registers for state preservation during resets, RTC Timestamping for data logging, and MPU/TAMPER for system integrity.
Challenges: 96kHz/24-bit High-Fidelity Sampling, Multi-layer Software Architecture, Power Management, Real-time Feature Extraction (MFCC), High-Noise Environment (80dB).
- Architect a modular firmware using ESP-IDF with a 3-layer stack: MCAL (Hardware Abstraction), Middleware (DSP/Feature Extraction), and Application (Logic & Predictive Models).
- Implement a high-speed data acquisition pipeline using I2S to offload the CPU, achieving a stable 96kHz sampling rate for precise acoustic fingerprinting.
- Design a precision Clock Tree utilizing an external 24.576MHz crystal and 74HCU04 IC to provide a clean master clock for the PCM1808 ADC, ensuring low-jitter audio capture.
- Develop a robust hardware front-end incorporating TL072 Op-amps, MAX9812, PJ-313B, TCT40-16R, and PCM1808 to process differential signals from industrial bearings (2000 RPM reference).
- Engineer power-efficient routines for battery operation (8-hour minimum) with integrated charging management and state-of-charge (SoC) monitoring.
Challenges: Peer-to-Peer (P2P) firmware distribution, Flash Memory Management, Bandwidth Optimization for IoT.
- Develop a comprehensive Over-The-Air (OTA) update system utilizing Device Firmware Update (DFU) protocols to enable seamless wireless software enhancements.
- Design a specialized Peer-to-Peer (P2P) update scenario where updated devices act as local sources to distribute 1MB firmware packages to neighboring targets, significantly reducing cloud bandwidth reliance.
- Optimize memory architecture for embedded targets, incorporating a Safe Rollback mechanism to restore the previous stable version in case of update failure or system instability.
- Design a user-centric management workflow, bridging the gap between Servers, Gateways, and end-user IoT devices through standardized communication.
