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Github actions: update the checkout action Latest #111: Commit 508575c pushed by xavierleroy
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AArch64 asm clobbers: recognize more register names (#576) Latest #110: Commit 0493127 pushed by xavierleroy
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Basic support for building multiple target architectures in parallel Latest #109: Commit cec2bd8 pushed by xavierleroy
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Clean up configure file Latest #108: Commit 90cf0ed pushed by xavierleroy
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More prudent handling of static names for string literals (#579) Latest #107: Commit 0737ca9 pushed by xavierleroy
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CI golf: rocq-prover:latest is currently unstable, use :9.1.1 instead Latest #106: Commit d9377f6 pushed by xavierleroy
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Update to Flocq 4.2.2 Latest #105: Commit 43320aa pushed by xavierleroy
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Branch relaxation: fix offset computation Latest #104: Commit e119538 pushed by xavierleroy
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Rocq 9.1.1 is supported Latest #103: Commit 1b71fec pushed by xavierleroy
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Compatibility with old OCaml versions Latest #102: Commit ebe31b0 pushed by xavierleroy
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Merge pull request #575 from AbsInt/relaxation Latest #101: Commit 14c0b59 pushed by xavierleroy
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Updates for release 3.17 Latest #100: Commit 7b1f02b pushed by xavierleroy
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Rocq/Coq 9.1.0 is supported Latest #99: Commit cb76888 pushed by xavierleroy
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Merge pull request #571 from AbsInt/extract-strings Latest #98: Commit 859d59b pushed by xavierleroy
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Latest Latest #97: Manually run by xavierleroy
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Avoid using is as a variable name Latest #96: Commit 4f8f2b1 pushed by xavierleroy
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AArch64 Asmexpand: use Asmgen.offset_representable in the expansion o… Latest #95: Commit 821abd5 pushed by xavierleroy
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Ceval.binop: take bit width of integer type into account for shifts Latest #94: Commit bf062de pushed by xavierleroy
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Ceval.binop: take bit width of integer type into account for shifts Latest #93: Commit ea88f42 pushed by xavierleroy
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Pass type of controlling switch expression into ctx. Latest #92: Commit f6a5780 pushed by xavierleroy
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cparser/ErrorReports.ml: remove the use of the deprecated library [Me… Latest #91: Commit af865ad pushed by xavierleroy
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macOS ARM: silence the 'redefining builtin macro' preprocessor warning Latest #90: Commit 2e1480a pushed by xavierleroy
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RISC-V: Favor the use of integer registers x10 to x15 Latest #89: Commit 51a8450 pushed by xavierleroy
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RISC-V: add missing Osel case for PrintOp Latest #88: Commit e671e45 pushed by xavierleroy
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Small fixes for unknown-warning-option. Latest #87: Commit a771939 pushed by xavierleroy
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