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Fix cache line alignment in cortex_m-cache package routines#454

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pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
pat-rogers:cache_maint_align
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Fix cache line alignment in cortex_m-cache package routines#454
pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
pat-rogers:cache_maint_align

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The generic Cache_Maintenance procedure used the raw Start address as the initial DCCMVAC write address without first aligning it down to a cache line boundary. If Start was not 32-byte aligned, the first cache line was only partially cleaned. Additionally, Len was not extended to account for the trimmed prefix bytes, leaving the final partial cache line unflushed.

Fix by aligning Op_Addr down to the nearest cache line boundary and extending Op_Size by the corresponding offset, ensuring all cache lines covering [Start, Start+Len) are cleaned.

The generic Cache_Maintenance procedure used the raw Start address as
the initial DCCMVAC write address without first aligning it down to a
cache line boundary. If Start was not 32-byte aligned, the first cache
line was only partially cleaned. Additionally, Len was not extended to
account for the trimmed prefix bytes, leaving the final partial cache
line unflushed.

Fix by aligning Op_Addr down to the nearest cache line boundary and
extending Op_Size by the corresponding offset, ensuring all cache lines
covering [Start, Start+Len) are cleaned.

correct new copyright date

formatting for readability
@pat-rogers pat-rogers changed the title Fix cache line alignment in Cache_Maintenance Fix cache line alignment in cortex_m-cache package routines Mar 22, 2026
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