Energy-Efficient Approximate Compressor Design for Error-Resilient DSP (OneMaj)

Based on the paper: Energy-Efficient approximate compressor design for error-resilient digital signal processing (International Journal of Electronics)

Overview

Approximate computing is a promising paradigm for designing low-power & high-speed hardware for error-resilient applications such as multimedia and digital signal processing (DSP). The 4:2 compressor is a critical building block in the Partial Product Reduction (PPR) stage of multipliers.

This paper proposes a novel logic expression based on a pseudo-majority gate to design two high-performance approximate 4:2 compressors (named OneMaj), which share the same logical relation while having two different hardware implementations. The proposed OneMaj designs drastically reduce the transistor count (down to 7 & 8 transistors) while improving power, delay, and layout area. To maintain high accuracy, a complementary Error Correction Module (ECM) is also provided.

Key Features

• Two Novel Hardware Designs: Complementary style-based (Design 1) and transmission gate style-based (Design 2).

• Extreme Efficiency: Built and evaluated using 7nm BSIM-CMG FinFET technology.

• High Robustness: Verified using comprehensive Monte Carlo simulations (±15% Gaussian distributions) against process variations like fin thickness and gate length.

• Application Level Verification: Demonstrated on an 8x8 inexact Dadda multiplier performing image multiplication.

• Verilog Implementation: Verilog implementations of all 4:2 compressors presented in the paper, including the proposed OneMaj and the related-works by Taheri, Moaiyeri, and Momeni, are provided. Moreover, the Verilog implementation of the 8×8 Wallace multiplier (OneMaj, Taheri, Moaiyeri, Momeni) and its related modules is provided for all the aforementioned 4:2 compressors.

• Verilog testbench for 4:2 compressors: A complete Verilog testbench (tbCompressor.v) is included for functional verification and comparative evaluation of four 4:2 compressors (OneMaj, Taheri, Moaiyeri, Momeni). The testbench is designed to:

  • apply all input combinations
  • compare the generated outputs
  • evaluate the behavior of each compressor
  • report the corresponding error metrics.

• Verilog Testbench for 8x8 Multipliers: tbMultiplier.v is a functional verification & comparative analysis of 8×8 multiplier architectures based on four different 4:2 compressors (OneMaj, Taheri, Moaiyeri, Momeni). This testbench automatically:

  • Feeds all possible input combinations (65,536 test vectors) to evaluate the design.
  • Evaluates & logs key performance metrics, including NMED, MRED, and PSNR, for each 4:2 compressor.

Summary of Results

• Area Efficiency: OneMaj (Design 1) reduces layout area by 55% to 81% compared to state-of-the-art approximate 4:2 compressors.
• Circuit Performance: OneMaj achieves ~39% lower delay and ~44% lower power consumption than prior approximate compressors.
• Image Quality: When integrated into an 8x8 multiplier, it improves average PSNR by 21% to 32% over related works, maintaining high visual structural similarity.

Citation

If you find this work useful in your research, please cite:

@article{avan2023energy,
  title={Energy-Efficient approximate compressor design for error-resilient digital signal processing},
  author={Avan, Amin and Taheri, MohammadReza and Moaiyeri, Mohammad Hossein and Navi, Keivan},
  journal={International Journal of Electronics},
  volume={110},
  number={9},
  pages={1555--1577},
  year={2023},
  publisher={Taylor \& Francis}
}