Update memory mapping, add video output, add functionality to debugger tool

.github/workflows/test.yml

@@ -2,7 +2,7 @@ name: Test
 
 on:
   push:
-    branches: ['**']
+    branches: [main]
   pull_request:
     branches: [main]
   workflow_dispatch:
@@ -17,7 +17,7 @@ jobs:
     runs-on: ubuntu-22.04
     strategy:
       matrix:
-        test-type: [unit, integration]
+        test-type: [unit, integration, vga]
       fail-fast: false
 
     steps:

CLAUDE.md

@@ -50,7 +50,7 @@ You don't need to manually read docs - the relevant rules load automatically bas
 
 - **DDR3**: Requires 200 MHz ref_clk, Bank 34 only (voltage isolation)
 - **UART**: 115200 baud @ 81.25 MHz ≈ 706 clocks/bit
-- **Memory map**: ROM < 0x1000, RAM ≥ 0x1000
+- **Memory map**: CPU base 0x80000000, ROM 0x80000000-0x80000FFF, RAM 0x80001000+, FB at end
 - **Pipeline**: 3-stage, no hazard detection (insert NOPs manually)
 
 ## Next Steps

docs/architecture.md

@@ -17,20 +17,25 @@ For detailed CPU internals, see [../ai/cpu-architecture.md](../ai/cpu-architectu
 ## Memory Map
 
 ```
-0x00000000 - 0x00000FFF: Boot ROM (4KB)
-0x10000000 - 0x1FFFFFFF: DDR3 RAM (via MIG, 256MB planned)
-0x20000000 - 0x2FFFFFFF: Framebuffer
-0x30000000 - 0x3FFFFFFF: Peripherals
-0x40000000 - 0x4FFFFFFF: Debug peripheral
+0x80000000 - 0x80000FFF: Boot ROM (4KB BRAM, internal to CPU)
+0x80001000 - 0x87F1DFFF: General RAM (~127MB DDR3 via MIG)
+0x87F1E000 - 0x87F8EFFF: Framebuffer 0 (462,848 bytes, 640x480x12bpp)
+0x87F8F000 - 0x87FFFFFF: Framebuffer 1 (462,848 bytes, 640x480x12bpp)
 ```
 
+Key addresses:
+- CPU_BASE_ADDR: 0x80000000 (PC starts here on reset)
+- ROM_BOUNDARY_ADDR: 0x80000FFF (last ROM address)
+- RAM_START_ADDR: 0x80001000 (first DDR3 address)
+- Framebuffers are 4K-aligned for DMA compatibility
+
 See [../ai/memory-map.md](../ai/memory-map.md) for detailed memory layout.
 
 ## Video System
 
 - VGA output: 640x480 @ 60Hz
 - Dual framebuffer for tear-free rendering
-- Pixel format: TBD (likely 8-bit indexed color)
+- Pixel format: 12-bit RGB (4 bits per channel)
 
 The video system uses double buffering to prevent tearing. While one framebuffer is being displayed, the CPU can write to the other. A register controls which buffer is active.
 

hdl/cpu/cpu.v

@@ -360,7 +360,9 @@ module cpu (
   wire w_Retire = w_Retire_Reg || w_Store_Commit;
 
   always @(posedge i_Clock) begin
-    if (!w_Reset) begin
+    if (w_Reset) begin
+      r_PC <= CPU_BASE_ADDR;
+    end else begin
       if(w_Debug_Write_PC_Enable && w_Pipeline_Flushed) begin
         r_PC <= w_Debug_Write_PC_Data;
       end else if (!w_Stall_S1 && w_Instruction_Valid && w_Enable_Instruction_Fetch) begin

hdl/cpu/cpu_core_params.vh

@@ -24,7 +24,13 @@ localparam REG_WRITE_NONE = 5;
 
 localparam CLOCK_FREQUENCY = 81_247_969;
 
-localparam ROM_BOUNDARY_ADDR = 32'hFFF;
+// Memory map constants
+localparam CPU_BASE_ADDR = 32'h80000000;
+localparam ROM_SIZE = 32'h00001000;
+localparam ROM_BOUNDARY_ADDR = CPU_BASE_ADDR + ROM_SIZE - 1;
+localparam FRAMEBUFFER_0_ADDR = 32'h87F1E000;
+localparam FRAMEBUFFER_1_ADDR = 32'h87F8F000;
+localparam FRAMEBUFFER_SIZE = 32'h71000;
 
 // UART parameters
 localparam UART_BAUD_RATE = 115200;

hdl/cpu/instruction_memory/instruction_memory_axi.v

@@ -4,7 +4,7 @@
 module instruction_memory_axi (
     input i_Reset,
     input i_Clock,
-    input i_Enable_Fetch, // Allows new fetch commands to be issued
+    input i_Enable_Fetch,  // Allows new fetch commands to be issued
     input [XLEN-1:0] i_Instruction_Addr,
     output reg [XLEN-1:0] o_Instruction,
     output o_Instruction_Valid,
@@ -28,7 +28,7 @@ module instruction_memory_axi (
     output s_axil_bready
 );
 
-  reg [31:0] rom[0:(ROM_BOUNDARY_ADDR>>2)];  // ROM Instruction Memory
+  reg [31:0] rom[0:(ROM_SIZE>>2)-1];  // ROM Instruction Memory (1024 words = 4KB)
 
   initial begin
     $readmemh("rom.mem", rom);
@@ -78,9 +78,12 @@ module instruction_memory_axi (
   assign o_Instruction_Valid = (r_State == READ_SUCCESS);
   // assign o_Fetch_Busy = (r_State != IDLE);
 
+  // Calculate offset from CPU base address for ROM indexing
+  wire [31:0] w_Rom_Offset = i_Instruction_Addr - CPU_BASE_ADDR;
+
   always @(*) begin
     if (i_Instruction_Addr <= ROM_BOUNDARY_ADDR && i_Enable_Fetch) begin
-      o_Instruction = rom[i_Instruction_Addr[11:2]];
+      o_Instruction = rom[w_Rom_Offset[11:2]];
     end else if (r_State == READ_SUCCESS) begin
       o_Instruction = s_axil_rdata;
     end else begin