Pinned Loading

1. BFloat16 BFloat16 Public

   RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

   Verilog 3

2. Systolic_MAC_with_DFT Systolic_MAC_with_DFT Public

   GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure

   Verilog 49

3. blake2_asic blake2_asic Public

   SKY130A implementatoin of the Blake2s hash algorithm

   Verilog 19 1

4. ethernet-physical-layer ethernet-physical-layer Public

   RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

   Tcl 34 12

5. Nasdaq-HFT-FPGA Nasdaq-HFT-FPGA Public

   RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

   C 81 27

6. Systolic_Array_with_DFT_v2 Systolic_Array_with_DFT_v2 Public

   IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

   Verilog 5