Skip to content
View Matthew-Otto's full-sized avatar

Highlights

  • Pro

Organizations

@SLAM-Lab @OKState-TWISTER

Block or report Matthew-Otto

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. RTL-IP RTL-IP Public

    Common SystemVerilog modules I use in my FPGA projects

    SystemVerilog 1

  2. Embedded-PTP-Timeserver Embedded-PTP-Timeserver Public

    STM32 based GPS-synchronized IEEE 1588 timeserver

    C

  3. Multicore-RTOS Multicore-RTOS Public

    A simple real-time OS for the Raspberry Pi Pico with multicore scheduling support.

    C 1

  4. Low-Latency-40GbE Low-Latency-40GbE Public

    A 40Gb Ethernet soft core MAC for the Stratix 10 series FPGAs targeting low latency

    SystemVerilog 1

  5. FPGA-ADSB-Decoder FPGA-ADSB-Decoder Public

    An FPGA based ADS-B receiver / decoder

    SystemVerilog

  6. OKState-TWISTER/TWISTER-Automation-Library OKState-TWISTER/TWISTER-Automation-Library Public

    A set of standardized classes and functions used to interface with the TWISTER system

    Python