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2 changes: 0 additions & 2 deletions source/SpinalHDL/Other language features/vhdl_generation.rst
Original file line number Diff line number Diff line change
Expand Up @@ -192,8 +192,6 @@ The syntax for command line arguments is:
Select the VHDL mode
--verilog
Select the Verilog mode
-d | --debug
Enter in debug mode directly
-o <value> | --targetDirectory <value>
Set the target directory

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