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Pull requests: SpinalHDL/VexRiscv

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Pull requests list

Tweaks to allow Compilation on both Scala 2.13 and 2.12
#470 opened Jan 25, 2026 by pete-restall Loading…
5
EmbeddedRiscvJtag support for system bus
#454 opened Jul 18, 2025 by craigjb Loading…
{I,D}BusSimplePlugin: don't rely on memoryTranslatorPortConfig != null
#307 opened Feb 26, 2023 by lschuermann • Draft
1
Regression Fix: Only Check IO Region
#146 opened Oct 22, 2020 by elliott-wen Loading…
2
Add memory 2 stage
#74 opened May 7, 2019 by tomverbeure Loading…
1
Add APB3 to AXI Stream peripheral to Murax (with FIFO)
#53 opened Jan 23, 2019 by eine Loading…
2
[WIP] Sphinx-RTD
#50 opened Jan 8, 2019 by wifasoi Loading…
5 tasks
1
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