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3 changes: 1 addition & 2 deletions flow/designs/asap7/aes-block/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,9 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.

export ABC_AREA = 1

export CORE_UTILIZATION = 40
export CORE_UTILIZATION = 47
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
export PLACE_DENSITY = 0.53

export BLOCKS ?= aes_rcon aes_sbox
export SYNTH_HIERARCHICAL = 1
Expand Down
16 changes: 8 additions & 8 deletions flow/designs/asap7/aes-block/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,27 +12,27 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 10573,
"value": 10549,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 919,
"value": 917,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 923,
"value": 917,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -124.0,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -5920.0,
"value": -10300.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -48,11 +48,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -150.0,
"value": -175.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -6750.0,
"value": -10600.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 52923,
"value": 50927,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -3780.0,
"value": -6230.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/nangate45/swerv/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ export PLATFORM = nangate45
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export CORE_UTILIZATION = 40
export CORE_UTILIZATION = 65
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 5

Expand Down
2 changes: 1 addition & 1 deletion flow/designs/nangate45/swerv/constraint.sdc
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design swerv

set clk_name core_clock
set clk_port_name clk
set clk_period 2.0
set clk_period 1.75
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
Expand Down
26 changes: 13 additions & 13 deletions flow/designs/nangate45/swerv/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -28,43 +28,43 @@
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -0.207,
"value": -0.387,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -9.64,
"value": -233.0,
"compare": ">="
},
"cts__timing__hold__ws": {
"value": -0.1,
"value": -0.0875,
"compare": ">="
},
"cts__timing__hold__tns": {
"value": -0.4,
"value": -0.35,
"compare": ">="
},
"globalroute__antenna_diodes_count": {
"value": 102,
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -0.224,
"value": -0.416,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -37.0,
"value": -305.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
"value": -0.1,
"value": -0.0875,
"compare": ">="
},
"globalroute__timing__hold__tns": {
"value": -0.4,
"value": -0.35,
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 2799467,
"value": 2659376,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -80,19 +80,19 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.235,
"value": -0.398,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -23.9,
"value": -234.0,
"compare": ">="
},
"finish__timing__hold__ws": {
"value": -0.1,
"value": -0.0875,
"compare": ">="
},
"finish__timing__hold__tns": {
"value": -0.4,
"value": -0.35,
"compare": ">="
},
"finish__design__instance__area": {
Expand Down
7 changes: 4 additions & 3 deletions flow/designs/sky130hd/chameleon/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,9 @@ export ABC_AREA = 1

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export DIE_AREA = 0 0 2920 3520
export CORE_AREA = 20 20 2900 3500
export CORE_UTILIZATION = 70
export CORE_ASPECT_RATIO = 1.3
export CORE_MARGIN = 2

export chameleon_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)

Expand All @@ -44,7 +45,7 @@ export ADDITIONAL_LEFS = $(chameleon_DIR)/lef/apb_sys_0.lef \
$(chameleon_DIR)/lef/DMC_32x16HC.lef \
$(chameleon_DIR)/lef/ibex_wrapper.lef

export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
#export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl

export FP_PDN_RAIL_WIDTH = 0.48
export FP_PDN_RAIL_OFFSET = 0
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/chameleon/constraint.sdc
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name core_clock
set clk_port_name HCLK
set clk_period 7.0
set clk_period 3
set clk_io_pct 0.1

set clk_port [get_ports $clk_port_name]
Expand Down
6 changes: 0 additions & 6 deletions flow/designs/sky130hd/chameleon/macro_placement.tcl

This file was deleted.

38 changes: 19 additions & 19 deletions flow/designs/sky130hd/chameleon/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,63 +8,63 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 6528032,
"value": 6489461,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 69712,
"value": 38946,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 6062,
"value": 3387,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 6062,
"value": 3387,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -0.35,
"value": -3.07,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -1.4,
"value": -13.2,
"compare": ">="
},
"cts__timing__hold__ws": {
"value": -0.35,
"value": -0.15,
"compare": ">="
},
"cts__timing__hold__tns": {
"value": -1.4,
"value": -0.6,
"compare": ">="
},
"globalroute__antenna_diodes_count": {
"value": 154,
"value": 100,
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -0.35,
"value": -2.85,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -1.4,
"value": -9.98,
"compare": ">="
},
"globalroute__timing__hold__ws": {
"value": -0.35,
"value": -0.15,
"compare": ">="
},
"globalroute__timing__hold__tns": {
"value": -1.4,
"value": -0.6,
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 771372,
"value": 724825,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -80,23 +80,23 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.35,
"value": -2.78,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1.4,
"value": -9.44,
"compare": ">="
},
"finish__timing__hold__ws": {
"value": -0.35,
"value": -0.15,
"compare": ">="
},
"finish__timing__hold__tns": {
"value": -1.4,
"value": -0.6,
"compare": ">="
},
"finish__design__instance__area": {
"value": 6531862,
"value": 6493440,
"compare": "<="
}
}
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/jpeg/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 50
export CORE_UTILIZATION = 55
export PLACE_DENSITY_LB_ADDON = 0.15
export TNS_END_PERCENT = 100

Expand Down
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/jpeg/constraint.sdc
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 5.5
set clk_period 5
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
Expand Down
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