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21 changes: 12 additions & 9 deletions src/rsz/src/RepairHold.cc
Original file line number Diff line number Diff line change
Expand Up @@ -572,7 +572,6 @@ void RepairHold::repairEndHold(sta::Vertex* end_vertex,
sta::PinSeq load_pins;
Slacks slacks;
mergeInit(slacks);
float excluded_cap = 0.0;
bool loads_have_out_port = false;
sta::VertexOutEdgeIterator edge_iter(path_vertex, graph_);
while (edge_iter.hasNext()) {
Expand All @@ -590,11 +589,6 @@ void RepairHold::repairEndHold(sta::Vertex* end_vertex,
&& network_->isTopLevelPort(load_pin)) {
loads_have_out_port = true;
}
} else {
sta::LibertyPort* load_port = network_->libertyPort(load_pin);
if (load_port) {
excluded_cap += load_port->capacitance();
}
}
}
}
Expand All @@ -611,9 +605,18 @@ void RepairHold::repairEndHold(sta::Vertex* end_vertex,
delayAsString(slacks[fall_index_][max_index_], sta_),
load_pins.size());
sta::Scene* corner = sta_->cmdScene();
float load_cap
= graph_delay_calc_->loadCap(end_vertex->pin(), corner, max_)
- excluded_cap;
// Compute load cap as the sum of the pin capacitances that the
// inserted hold buffer will drive. Using loadCap on the driver pin
// would include the full original-net parasitics which are absent
// on the post-split net, causing the guard below to over-reject
// valid insertions.
float load_cap = 0.0;
for (const sta::Pin* load_pin : load_pins) {
sta::LibertyPort* load_port = network_->libertyPort(load_pin);
if (load_port) {
load_cap += load_port->capacitance();
}
}
sta::ArcDelay buffer_delays[sta::RiseFall::index_count];
sta::Slew buffer_slews[sta::RiseFall::index_count];
resizer_->bufferDelays(buffer_cell,
Expand Down
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