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3 changes: 3 additions & 0 deletions src/cts/src/TritonCTS.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,7 @@
#include "sta/Vector.hh"
#include "stt/SteinerTreeBuilder.h"
#include "utl/Logger.h"
#include "utl/timer.h"

namespace cts {

Expand Down Expand Up @@ -85,6 +86,7 @@ TritonCTS::~TritonCTS()

void TritonCTS::runTritonCts()
{
utl::Timer timer;
odb::dbChip* chip = db_->getChip();
odb::dbBlock* block = chip->getBlock();
options_->addOwner(block);
Expand Down Expand Up @@ -121,6 +123,7 @@ void TritonCTS::runTritonCts()
regTreeRootBufIndex_ = 0;
delayBufIndex_ = 0;
options_->removeOwner();
logger_->info(CTS, 500, "Runtime: {:.2f}s", timer.elapsed());
}

TreeBuilder* TritonCTS::addBuilder(CtsOptions* options,
Expand Down
3 changes: 3 additions & 0 deletions src/dpl/src/Opendp.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
#include "odb/util.h"
#include "util/journal.h"
#include "utl/Logger.h"
#include "utl/timer.h"

namespace dpl {

Expand Down Expand Up @@ -117,6 +118,7 @@ void Opendp::detailedPlacement(const int max_displacement_x,
const std::string& report_file_name,
bool incremental)
{
utl::Timer timer;
incremental_ = incremental;
importDb();
adjustNodesOrient();
Expand Down Expand Up @@ -162,6 +164,7 @@ void Opendp::detailedPlacement(const int max_displacement_x,
}
logger_->error(DPL, 36, "Detailed placement failed.");
}
logger_->info(DPL, 500, "Runtime: {:.2f}s", timer.elapsed());
}

void Opendp::updateDbInstLocations()
Expand Down
3 changes: 3 additions & 0 deletions src/drt/src/TritonRoute.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@
#include "utl/CallBackHandler.h"
#include "utl/Logger.h"
#include "utl/ScopedTemporaryFile.h"
#include "utl/timer.h"

using odb::dbTechLayerType;

Expand Down Expand Up @@ -977,6 +978,7 @@ void TritonRoute::sendDesignUpdates(const std::string& router_cfg_path,

int TritonRoute::main()
{
utl::Timer timer;
// Just to verify that OMP support is compiled in correctly.
omp_set_num_threads(2);
#pragma omp parallel
Expand Down Expand Up @@ -1075,6 +1077,7 @@ int TritonRoute::main()
if (!router_cfg_->SINGLE_STEP_DR) {
endFR();
}
logger_->info(utl::DRT, 501, "Runtime: {:.2f}s", timer.elapsed());
return 0;
}

Expand Down
3 changes: 3 additions & 0 deletions src/gpl/src/replace.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@
#include "sta/StaMain.hh"
#include "timingBase.h"
#include "utl/Logger.h"
#include "utl/timer.h"
#include "utl/validation.h"

namespace gpl {
Expand Down Expand Up @@ -155,8 +156,10 @@ void Replace::doIncrementalPlace(const int threads, const PlaceOptions& options)

void Replace::doPlace(const int threads, const PlaceOptions& options)
{
utl::Timer timer;
doInitialPlace(threads, options);
doNesterovPlace(threads, options);
log_->info(GPL, 500, "Runtime: {:.2f}s", timer.elapsed());
}

void Replace::doInitialPlace(const int threads, const PlaceOptions& options)
Expand Down
14 changes: 6 additions & 8 deletions src/grt/src/GlobalRouter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@
#include "grt/GlobalRouter.h"

#include <algorithm>
#include <chrono>
#include <cmath>
#include <cstdint>
#include <cstring>
Expand Down Expand Up @@ -59,6 +58,7 @@
#include "utl/CallBackHandler.h"
#include "utl/Logger.h"
#include "utl/algorithms.h"
#include "utl/timer.h"

namespace grt {

Expand Down Expand Up @@ -342,7 +342,7 @@ void GlobalRouter::endIncremental(bool save_guides)

void GlobalRouter::globalRoute(bool save_guides)
{
auto start = std::chrono::steady_clock::now();
utl::Timer timer;
bool has_routable_nets = false;

for (auto net : db_->getChip()->getBlock()->getNets()) {
Expand Down Expand Up @@ -389,13 +389,11 @@ void GlobalRouter::globalRoute(bool save_guides)
}

finishGlobalRouting(save_guides);
auto end = std::chrono::steady_clock::now();
if (verbose_) {
auto runtime
= std::chrono::duration_cast<std::chrono::seconds>(end - start);
int hour = runtime.count() / 3600;
int min = (runtime.count() % 3600) / 60;
int sec = runtime.count() % 60;
const int elapsed = static_cast<int>(timer.elapsed());
const int hour = elapsed / 3600;
const int min = (elapsed % 3600) / 60;
const int sec = elapsed % 60;
logger_->info(
GRT, 303, "Global routing runtime = {:02}:{:02}:{:02}", hour, min, sec);
}
Expand Down
5 changes: 5 additions & 0 deletions src/ifp/src/InitFloorplan.cc
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
#include "sta/StringUtil.hh"
#include "upf/upf.h"
#include "utl/Logger.h"
#include "utl/timer.h"
#include "utl/validation.h"

namespace ifp {
Expand Down Expand Up @@ -108,6 +109,7 @@ void InitFloorplan::initFloorplan(
const std::set<odb::dbSite*>& flipped_sites,
const int gap)
{
utl::Timer timer;
checkGap(gap);

makeDieUtilization(utilization,
Expand All @@ -125,6 +127,7 @@ void InitFloorplan::initFloorplan(
row_parity,
flipped_sites,
gap);
logger_->info(IFP, 500, "Runtime: {:.2f}s", timer.elapsed());
}

// The base_site determines the single-height rows. For hybrid rows it is
Expand All @@ -138,10 +141,12 @@ void InitFloorplan::initFloorplan(
const std::set<odb::dbSite*>& flipped_sites,
const int gap)
{
utl::Timer timer;
checkGap(gap);

makeDie(die);
makeRows(core, base_site, additional_sites, row_parity, flipped_sites, gap);
logger_->info(IFP, 501, "Runtime: {:.2f}s", timer.elapsed());
}

void InitFloorplan::makeDieUtilization(double utilization,
Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan1.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan2.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan3.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan4.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan5.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

tech = Tech()
tech.readLef("Nangate45/Nangate45.lef")
design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan6.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan7.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan8.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan9.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("sky130hd/sky130_fd_sc_hd_merged.lef")
tech.readLiberty("sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg2.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan_dbl_row.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
tech.readLef("init_floorplan_dbl_row.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan_flip_sites.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/init_floorplan_gap.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
tech.readLef("init_floorplan_gap.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks1.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks2.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks3.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks4.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks5.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/make_tracks6.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
tech = Tech()
tech.readLef("Nangate45/Nangate45.lef")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/manpage.py
2 changes: 1 addition & 1 deletion src/ifp/test/md_roff_compat.py
2 changes: 1 addition & 1 deletion src/ifp/test/placement_blockage1.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/placement_blockage2.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("reg1.v")
design.link("top")

Expand Down
2 changes: 1 addition & 1 deletion src/ifp/test/tiecells.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
tech.readLef("Nangate45/Nangate45.lef")
tech.readLiberty("Nangate45/Nangate45_typ.lib")

design = Design(tech)
design = helpers.make_design(tech)
design.readVerilog("tiecells.v")
design.link("top")

Expand Down
3 changes: 3 additions & 0 deletions src/mpl/src/rtl_mp.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
#include "odb/db.h"
#include "odb/geom.h"
#include "utl/Logger.h"
#include "utl/timer.h"

namespace mpl {
using std::string;
Expand Down Expand Up @@ -58,6 +59,7 @@ bool MacroPlacer::place(const int num_threads,
const char* report_directory,
const bool keep_clustering_data)
{
utl::Timer timer;
hier_rtlmp_->init();
hier_rtlmp_->setClusterSize(
max_num_macro, min_num_macro, max_num_inst, min_num_inst);
Expand All @@ -84,6 +86,7 @@ bool MacroPlacer::place(const int num_threads,

hier_rtlmp_->run();

logger_->info(MPL, 500, "Runtime: {:.2f}s", timer.elapsed());
return true;
}

Expand Down
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