Fix for issue 9439 report_checks crash

search/PathGroup.cc

@@ -426,8 +426,14 @@ PathGroups::pathGroups(const PathEnd *path_end) const
   // GroupPaths have precedence.
   else if (!group_paths.empty()) {
     for (ExceptionPath *group_path : group_paths) {
-      if (group_path->isDefault())
-	path_groups.push_back(path_delay_[mm_index]);
+      if (group_path->isDefault()) {
+        // NULL check needed as PathGroups::makeGroups would have made this
+        // nullptr if report_checks was asked with a valid non-default
+        // "-path_group"
+        if (path_delay_[mm_index] != nullptr) {
+          path_groups.push_back(path_delay_[mm_index]);
+        }
+      }
       else {
 	const char *group_name = group_path->name();
 	PathGroup *group = findPathGroup(group_name, min_max);

test/regression_vars.tcl

@@ -161,6 +161,7 @@ record_public_tests {
   path_group_names
   power_json
   prima3
+  report_checks_default_path_grp
   report_checks_sorted
   report_checks_src_attr
   report_json1

test/report_checks_default_path_grp.ok

@@ -0,0 +1,85 @@
+Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
+Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+
+    Cap    Slew   Delay    Time   Description                          Src Attr
+---------------------------------------------------------------------------------------------------------------
+           0.00    0.00    0.00   clock clk (rise edge)
+                   0.00    0.00   clock network delay (ideal)
+           0.00    0.00    0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
+   0.00    0.04    0.33    0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
+                                  mid (net)                            synthesis/tests/counter.v:22.3-28.6
+           0.04    0.00    0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
+                           0.33   data arrival time
+
+           0.00   10.00   10.00   clock clk (rise edge)
+                   0.00   10.00   clock network delay (ideal)
+                   0.00   10.00   clock reconvergence pessimism
+                          10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
+                  -0.12    9.88   library setup time
+                           9.88   data required time
+---------------------------------------------------------------------------------------------------------------
+                           9.88   data required time
+                          -0.33   data arrival time
+---------------------------------------------------------------------------------------------------------------
+                           9.55   slack (MET)
+
+
+Creating path group with 2 cells
+clk crash_group asynchronous {path delay} {gated clock} unconstrained
+Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
+Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
+Path Group: crash_group
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
+   0.33    0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)
+   0.00    0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1)
+           0.33   data arrival time
+
+  10.00   10.00   clock clk (rise edge)
+   0.00   10.00   clock network delay (ideal)
+   0.00   10.00   clock reconvergence pessimism
+          10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
+  -0.12    9.88   library setup time
+           9.88   data required time
+---------------------------------------------------------
+           9.88   data required time
+          -0.33   data arrival time
+---------------------------------------------------------
+           9.55   slack (MET)
+
+
+clk crash_group asynchronous {path delay} {gated clock} unconstrained
+Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
+Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
+Path Group: crash_group
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
+   0.33    0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)
+   0.00    0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1)
+           0.33   data arrival time
+
+  10.00   10.00   clock clk (rise edge)
+   0.00   10.00   clock network delay (ideal)
+   0.00   10.00   clock reconvergence pessimism
+          10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
+  -0.12    9.88   library setup time
+           9.88   data required time
+---------------------------------------------------------
+           9.88   data required time
+          -0.33   data arrival time
+---------------------------------------------------------
+           9.55   slack (MET)
+
+

test/report_checks_default_path_grp.tcl

@@ -0,0 +1,23 @@
+# report_checks all fields enabled
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_attribute.v
+link_design counter
+
+create_clock -name clk -period 10 clk
+set_input_delay -clock clk 0 [all_inputs -no_clocks]
+report_checks -path_group clk -fields {capacitance slew input_pin net src_attr}
+
+set module_name "_141"
+set module_pattern "${module_name}*"
+set all_module_cells [get_cells $module_pattern]
+puts "Creating path group with [llength $all_module_cells] cells"
+
+group_path -from $all_module_cells -to $all_module_cells -name "crash_group"
+set x [sta::path_group_names]
+puts $x
+report_checks -path_group "crash_group"
+
+group_path -from $all_module_cells -to $all_module_cells -default
+set x [sta::path_group_names]
+puts $x
+report_checks -path_group "crash_group"