Attempt to fix LVS mismatch and SRAM creation with banks for sky130

[ruhai-lin]

✅I have read CONTRIBUTING.md and am submitting this PR against the dev branch as requested.

Background

While compiling the sky130 macro config sky130_sram_1kbyte_1rw_32x256_8, I ran:

python sram_compiler.py macros/sram_configs/sky130_sram_1kbyte_1rw_32x256_8.py

and consistently hit two known failures that have been discussed publicly:

LVS mismatch:

#217

Could not find bl net in timing paths:

#228

https://web.open-source-silicon.dev/t/27045118/hello-everyone-i-am-exploring-openram-and-want-to-create-a-r

a more detailed log is:

** Start: 02/19/2026 10:34:31 
Technology: sky130 
Total size: 8192 bits 
Word size: 32 
Words: 256 
Banks: 1 
Write size: 8 
RW ports: 1 
R-only ports: 0 
W-only ports: 0 
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). Only generating nominal corner timing. Words per row: None 
Output files are: /home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.lvs 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.sp 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.v 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.lib 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.py 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.html 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.log 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.lef 
/home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.gds 
** Submodules: 143.6 seconds 
** Placement: 0.0 seconds 
** Routing: 786.1 seconds 
ERROR: file magic.py: line 385: sky130_sram_1kbytes_1rw_32x256_8 LVS mismatch (results in /tmp/openram_rlin50_4126947_temp/sky130_sram_1kbytes_1rw_32x256_8.lvs.report) 
** Verification: 18140.4 seconds 
** SRAM creation: 19070.1 seconds 
SP: Writing to /home/rlin50/Projects/OpenRAM_Study/OpenRAM/macro/sky130_sram_1kbytes_1rw_32x256_8/sky130_sram_1kbytes_1rw_32x256_8.sp 
** Spice writing: 0.2 seconds DELAY: Writing stimulus... 
ERROR: file simulation.py: line 605: Could not find bl net in timing paths. Traceback (most recent call last): File "sram_compiler.py", line 76, in <module> s.save() File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/sram.py", line 130, in save d.analysis_init(probe_address, probe_data) File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init self.set_internal_spice_names() File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/characterizer/simulation.py", line 624, in get_bl_name bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/characterizer/simulation.py", line 605, in get_alias_in_path debug.error("Could not find {} net in timing paths.".format(internal_net), 1) File "/home/rlin50/Projects/OpenRAM_Study/OpenRAM/compiler/debug.py", line 48, in error assert return_value == 0 AssertionError

Root causes maybe

The LVS mismatch is driven by a sky130 col_cap / related array pin-order / connection-order mismatch (i.e., instance connection order does not match the expected port order), which causes top-level matching to fail.

The characterization failure is caused by the address bit-order assumption used by the characterizer did not match the generated netlist, leading to wrong probe row/col selection and thus missing BL paths.

What this PR changes

1. Align col_cap / bitcell base array port ordering with the actual instance connection order so that LVS top-level matching succeeds for this macro.
   Affected files:
   technology/sky130/sky130_bitcell_base_array.py
technology/sky130/sky130_col_cap_array.py

2. Fix address bit-order parsing used by the characterizer so probe row/col selection matches the generated netlist conventions.
   Affected files:
   compiler/characterizer/simulation.py
compiler/characterizer/delay.py
compiler/characterizer/trim_spice.py

Testing

I tested this on my stable/local branch again with:

python sram_compiler.py macros/sram_configs/sky130_sram_1kbyte_1rw_32x256_8.py

and the flow completes successfully for this configuration.

Limitations / request for review

I did not have knowledge or time to test other configs, and I also did not verify compatibility with the latest dev branch changes beyond my local environment.

Since I’m not deeply familiar with OpenRAM internals, I would appreciate maintainer review on whether these fixes are correctly scoped and whether any gating/generalization is preferred.