Parity bit in the uart VCs

[nicdes]

Implementation of the parity bit (none, even, odd, mark, space) in the uart VCs.

• Adds a parity_mode in the uart_master_t and uart_slave_t records (uart_pkg.vhd).
• uart_master.vhd sends the parity bit (if parity_mode /= none).
• uart_slave.vhd checks the parity bit and logs errors on the "uart" logger.
• run.py generates the configurations for the "test parity" test case.
• tb_uart.vhd mocks the uart logger and checks for expected failure when master and slave use different parity modes.

Could be related to PR #495.