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Ensure rounding flag is properly emitted on some x86 floating point instructions #8015

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Ensure rounding flag is properly emitted on some x86 floating point instructions #8015

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6 changes: 5 additions & 1 deletion arch/x86/arch_x86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2124,7 +2124,7 @@ size_t X86CommonArchitecture::GetFlagWriteLowLevelIL(BNLowLevelILOperation op, s
case IL_FLAG_O:
return il.Const(0, 0);
case IL_FLAG_A:
return il.Undefined();
return il.Unimplemented();
}
break;
case LLIL_MULU_DP:
Expand Down Expand Up @@ -2152,6 +2152,10 @@ size_t X86CommonArchitecture::GetFlagWriteLowLevelIL(BNLowLevelILOperation op, s
break;
}
}

if (flagWriteType == IL_FLAGWRITE_X87RND && flag == IL_FLAG_C1)
return il.Unimplemented();

if (((flagWriteType == IL_FLAGWRITE_X87COM) || (flagWriteType == IL_FLAGWRITE_X87C1Z)) && (flag == IL_FLAG_C1))
return il.Const(0, 0);
return Architecture::GetFlagWriteLowLevelIL(op, size, flagWriteType, flag, operands, operandCount, il);
Expand Down
8 changes: 4 additions & 4 deletions arch/x86/arch_x86_intrinsics.cpp
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Expand Up @@ -5183,9 +5183,9 @@ vector<NameAndType> X86CommonArchitecture::GetIntrinsicInputs(uint32_t intrinsic

vector<Confidence<Ref<Type>>> X86CommonArchitecture::GetIntrinsicOutputs(uint32_t intrinsic)
{
static const vector<Confidence<Ref<Type>>> singleFloat10 { Type::FloatType(10)->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> singleFloat10Bool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> singleInt10 { Type::IntegerType(10, false)->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> float10Bool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> float10BoolBool { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> doubleFloat10Bool { Type::FloatType(10)->SetIgnored(true), Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> float10BoolInt1 { Type::FloatType(10)->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::IntegerType(1, false)->SetIgnored(true) };
static const vector<Confidence<Ref<Type>>> quadBool { Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true), Type::BoolType()->SetIgnored(true) };
Expand All @@ -5202,13 +5202,13 @@ vector<Confidence<Ref<Type>>> X86CommonArchitecture::GetIntrinsicOutputs(uint32_
case INTRINSIC_FSCALE:
case INTRINSIC_FYL2X:
case INTRINSIC_FYL2XP1:
return singleFloat10;
return singleFloat10Bool;
case INTRINSIC_FBST:
return singleInt10;
case INTRINSIC_FSIN:
case INTRINSIC_FCOS:
case INTRINSIC_FPTAN:
return float10Bool;
return float10BoolBool;
case INTRINSIC_FSINCOS:
return doubleFloat10Bool;
case INTRINSIC_FPREM:
Expand Down
20 changes: 10 additions & 10 deletions arch/x86/il.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4742,13 +4742,13 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
break;

case XED_ICLASS_F2XM1:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1)},
INTRINSIC_F2XM1, vector<ExprId> { il.Register(10, XED_REG_ST0) }, IL_FLAGWRITE_X87RND));
break;

case XED_ICLASS_FBLD:
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1) },
INTRINSIC_FBLD, vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) }, IL_FLAGWRITE_X87C1Z));
break;

Expand All @@ -4764,25 +4764,25 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev

case XED_ICLASS_FSIN:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSIN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSIN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
IL_FLAGWRITE_X87RND));
break;

case XED_ICLASS_FCOS:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FCOS, vector<ExprId> { il.Register(10, XED_REG_ST0) },
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FCOS, vector<ExprId> { il.Register(10, XED_REG_ST0) },
IL_FLAGWRITE_X87RND));
break;

case XED_ICLASS_FSINCOS:
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1),
RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSINCOS,
RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSINCOS,
vector<ExprId> { il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND));
break;

case XED_ICLASS_FPATAN:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1) },
INTRINSIC_FPATAN, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND));
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
Expand Down Expand Up @@ -4822,7 +4822,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev

case XED_ICLASS_FPTAN:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0),
RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FPTAN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FPTAN, vector<ExprId> { il.Register(10, XED_REG_ST0) },
IL_FLAGWRITE_X87RND));
il.AddInstruction(il.If(il.Flag(IL_FLAG_C2), doneLabel, falseLabel));
il.MarkLabel(falseLabel);
Expand All @@ -4836,7 +4836,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
break;

case XED_ICLASS_FSCALE:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C1) },
INTRINSIC_FSCALE, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
IL_FLAGWRITE_X87RND));
break;
Expand All @@ -4855,15 +4855,15 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
break;

case XED_ICLASS_FYL2X:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1)},
INTRINSIC_FYL2X, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
IL_FLAGWRITE_X87RND));
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));
il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1))));
break;

case XED_ICLASS_FYL2XP1:
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) },
il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), RegisterOrFlag::Flag(IL_FLAG_C1)},
INTRINSIC_FYL2XP1, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) },
IL_FLAGWRITE_X87RND));
il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0));
Expand Down
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