SERCOM async/DMA for Wire, SPI, and UART by crabel99 · Pull Request #385 · adafruit/ArduinoCore-samd

crabel99 · 2026-02-17T05:05:42Z

Related Issue: #382

SERCOM Async/DMA API Comparison: sercom-async-dma vs Master

Executive Summary

Motivation

The SAMD21/SAMD51 SERCOM peripherals support hardware-accelerated DMA transfers, but the Arduino core's synchronous blocking APIs don't expose this capability. This creates performance bottlenecks in applications that need to communicate with multiple peripherals efficiently. The master branch Wire library had internal async/DMA support, but the API remained entirely synchronous, and the patterns weren't extended to SPI or UART.

This branch extends transparent async/DMA operation across all three major SERCOM interfaces (Wire/I2C, SPI, UART) while maintaining 100% backward compatibility with existing synchronous code.

Design Intent

Primary Goals:

Zero Breaking Changes: All existing synchronous code must work identically without modification
Transparent DMA: Hardware acceleration should be internal - no exposed DMA/fallback helper functions
Unified API Pattern: All three interfaces should follow the same async design pattern
Opt-in Async: Applications can choose async operation by providing callbacks; default behavior is synchronous
Transaction Pooling: Match SERCOM hardware queue depth (8 transactions) for optimal throughput

Key Design Decision:

SERCOM APIs are entirely async-only; synchronous behavior is provided only at the protocol level (Wire/SPI/UART) via callback defaults.

Non-Goals:

Exposing low-level DMA control to users
Creating separate async-only APIs (e.g., separate writeAsync() methods)
Changing the behavioral contract of existing APIs

Philosophy

"Seamless by default, async by choice"

The API design follows a simple principle: when a callback is provided (!= nullptr), the operation is asynchronous and returns immediately; when no callback is provided (== nullptr), the operation is synchronous and blocks until complete. This allows:

Legacy code: Works unchanged with zero modifications
Gradual migration: Applications can adopt async selectively, one call at a time
Clean interfaces: No API surface area explosion with separate methods for each mode
Internal optimization: DMA acceleration happens transparently when USE_ZERODMA is defined

The transaction pool architecture (8 transactions matching SERCOM queue depth) enables efficient pipelining of operations without exposing queue management to applications.

Hardware Testing Status

✅ Tested Configurations

Interface	Mode	Device	Test Coverage	Status
SPI	Master	TMC5130A Stepper Driver	6/6 tests passing	✅ Hardware validated
UART	N/A	Hardware loopback	5/5 tests passing	✅ Hardware validated
Wire (I2C)	Master	MCP9600 Temperature Sensor	Sync/async/DMA/non-DMA mixed transactions + loader unit tests	✅ Hardware validated

⚠️ Untested Configurations

Interface	Mode/Feature	Reason
Wire (I2C)	Slave	No hardware test setup available
Wire (I2C)	High-speed mode (Hs-mode)	No Hs-mode capable device available for full end-to-end testing
Wire (I2C)	10-bit addressing	No 10-bit address device available for testing
SPI	Slave	No hardware test setup available
UART	N/A	UART is peer-to-peer (no master/slave concept)

Testing Notes:

SPI master mode has been validated with a real TMC5130A stepper motor driver, covering read/write/bulk transfer operations
UART has been tested with hardware loopback configuration, validating both sync and async read/write paths
Wire (I2C) has been fully validated with an MCP9600 temperature sensor, including:
- Synchronous blocking operations (legacy API compatibility)
- Asynchronous callback-based operations
- DMA-accelerated transfers (USE_ZERODMA enabled)
- Non-DMA fallback paths (USE_ZERODMA disabled)
- Mixed transaction scenarios (sync/async interleaved)
- Loader transaction builder unit tests
- SCLSM (SCL stretch mode) operation validated
No slave mode testing has been performed for any interface
Hs-mode (High-speed I2C): SCLSM flag validated but full Hs-mode communication not tested (requires Hs-mode capable device)
10-bit addressing: API support added but not hardware validated (no 10-bit device available)
All tests use the Unity framework and run on SAMD21 hardware (test_simio_m0 environment)
DMA acceleration (USE_ZERODMA) has been tested alongside fallback paths (without DMA library)

Recommended Pre-Merge Validation

Before merging to master, reviewers should consider:

✅ API compatibility: All existing synchronous code patterns work unchanged (verified)
✅ I2C device testing: Wire tested with MCP9600 sensor covering sync/async/DMA/non-DMA paths
⚠️ Slave mode validation: Test Wire and SPI slave modes if these are supported use cases
⚠️ Multi-SERCOM stress testing: Validate concurrent async operations across multiple SERCOM instances
⚠️ Production workload: Test with real application workloads beyond synthetic tests

Known Limitations & Future Development

Current Limitations (SAMD21/SAMD51 Silicon Errata):

Hs-mode restrictions: High-speed I2C requires SCLSM=1, which prevents reliable STOP/RESTART commands in interrupt-driven byte mode. Therefore, Hs-mode is DMA-only and STOP-only (no repeated starts)
QCEN restriction: Quick Command Enable (QCEN) must not be enabled when SCLSM=1 (causes bus errors per silicon errata)
DMA completion window: Wire transactions experience ~350 processor cycles after DMA completion where the hardware is in an unstable state. Initiating a new DMA transaction during this window causes hardware faults. The implementation handles this through appropriate completion signaling and transaction scheduling
These restrictions are documented in Wire.h and handled by the implementation

Future Development Roadmap:

Hardware CRC Integration (Requires DMA):
- SAMD21/SAMD51 peripherals support hardware CRC calculation during DMA transfers
- Integration planned for protocols requiring CRC (e.g., SPI with CRC checksums)
- Will leverage existing DMA infrastructure added in this branch
- Target use case: High-reliability communication with industrial sensors/actuators
Additional Testing:
- Hs-mode I2C with compatible devices
- 10-bit I2C addressing validation
- Slave mode for Wire and SPI
- Multi-SERCOM concurrent stress testing
Performance Optimization:
- Benchmark DMA vs non-DMA paths with various transfer sizes
- Transaction pool tuning for specific workloads
- Memory footprint optimization
SAMD51 Clock Selection Enhancement:
- Automatic SERCOM clock selection based on requested bus speed
- Direct SERCOM API for clock configuration (currently abstracted)
- Optimize power consumption by selecting appropriate clock sources
- Improve precision for non-standard baud rates
Strict I2C Pad Validation:
- Enforce SDA/SCL pad pairing rules from datasheet pinmux tables
- Provide clearer diagnostics when invalid SERCOM/pad combinations are requested
Optional Companion Libraries (Future):
- SerialRTT: Lightweight RTT-based serial transport Stream for low-overhead debug I/O
- DebugUtils: Common debug helpers for native and embedded testing plus Unity test support, pre-test scripts, and example PlatformIO configs

API Change Summary

Quick reference of what changed across the three interfaces:

Interface	Sync API Changes	New Async Capabilities	Backward Compatible?
Wire	None (defaults preserved)	`endTransmission()` + `requestFrom()` now accept callbacks	✅ Yes (callbacks default to nullptr)
UART	None (existing methods unchanged)	NEW: `read(buffer, size, callback)` and `write(buffer, size, callback)`	✅ Yes (additions only)
SPI	None (defaults preserved)	`transfer()` now accepts callbacks	✅ Yes (callbacks default to nullptr)

Detailed API Comparison

Wire API Changes

Master Branch (Original)

class TwoWire : public Stream {
  public:
    TwoWire(SERCOM *s, uint8_t pinSDA, uint8_t pinSCL);
    void begin();
    void begin(uint8_t, bool enableGeneralCall = false);
    void end();
    void setClock(uint32_t);

    void beginTransmission(uint8_t);
    uint8_t endTransmission(bool stopBit);
    uint8_t endTransmission(void);

    uint8_t requestFrom(uint8_t address, size_t quantity, bool stopBit);
    uint8_t requestFrom(uint8_t address, size_t quantity);

    size_t write(uint8_t data);
    size_t write(const uint8_t * data, size_t quantity);

    virtual int available(void);
    virtual int read(void);
    virtual int peek(void);
    virtual void flush(void);
    void onReceive(void(*)(int));
    void onRequest(void(*)(void));

    inline size_t write(unsigned long n) { return write((uint8_t)n); }
    inline size_t write(long n) { return write((uint8_t)n); }
    inline size_t write(unsigned int n) { return write((uint8_t)n); }
    inline size_t write(int n) { return write((uint8_t)n); }
    using Print::write;

    void onService(void);
};

Note: Master branch Wire already had some async operation support through internal transaction mechanisms, but the API was entirely synchronous (blocking).

sercom-async-dma Branch (Enhanced)

class TwoWire : public Stream {
  public:
    TwoWire(SERCOM *s, uint8_t pinSDA, uint8_t pinSCL);
    void begin();
    void begin(uint16_t, bool enableGeneralCall = false, uint8_t speed = 0x0, bool enable10Bit = false);
    void begin(uint8_t, bool enableGeneralCall = false);
    void end();
    void setClock(uint32_t);

    void beginTransmission(uint8_t);
    
    // MODIFIED: Added async callback support
    // If onComplete is nullptr, blocks for legacy sync behavior
    // If onComplete is non-null, enqueues and returns immediately (async)
    uint8_t endTransmission(bool stopBit = true,
                            void (*onComplete)(void* user, int status) = nullptr,
                            void* user = nullptr);

    // MODIFIED: Added async callback support + external buffer support
    // If onComplete is nullptr, blocks for legacy sync behavior
    // If onComplete is non-null, enqueues and returns immediately (async)
    // If rxBuffer is nullptr, internal buffer is used; otherwise rxBuffer is used
    uint8_t requestFrom(uint8_t address, size_t quantity, bool stopBit = true,
                        uint8_t* rxBuffer = nullptr,
                        void (*onComplete)(void* user, int status) = nullptr,
                        void* user = nullptr);

    size_t write(uint8_t data);
    
    // MODIFIED: Added setExternal parameter for zero-copy async
    // When setExternal=true, data is used directly (zero-copy) and
    // quantity is treated as both length and capacity
    size_t write(const uint8_t * data, size_t quantity, bool setExternal = false);

    virtual int available(void);
    virtual int read(void);
    virtual int peek(void);
    virtual void flush(void);
    void onReceive(void(*)(int));
    void onRequest(void(*)(void));
    
    // NEW: External buffer support for zero-copy async operations
    void setRxBuffer(uint8_t* buffer, size_t length);
    void setTxBuffer(uint8_t* buffer, size_t length);
    void clearRxBuffer(void);
    void resetRxBuffer(void);
    uint8_t* getRxBuffer(void);
    size_t getRxLength(void) const;

    inline size_t write(unsigned long n) { return write((uint8_t)n); }
    inline size_t write(long n) { return write((uint8_t)n); }
    inline size_t write(unsigned int n) { return write((uint8_t)n); }
    inline size_t write(int n) { return write((uint8_t)n); }
    using Print::write;

    inline void onService(void);
};

Wire API Summary

Feature	Master	sercom-async-dma	Notes
beginTransmission	✅ `beginTransmission(addr)`	✅ (unchanged)	Start multi-stage transaction
endTransmission (sync)	✅ `endTransmission(stop)`	✅ `endTransmission(stop=true)`	Legacy blocking behavior when callback=nullptr
endTransmission (async)	❌ N/A	✅ `endTransmission(stop, callback, user)`	NEW: Non-blocking with callback
requestFrom (sync)	✅ `requestFrom(addr, qty, stop)`	✅ `requestFrom(addr, qty, stop=true)`	Legacy blocking behavior when callback=nullptr
requestFrom (async)	❌ N/A	✅ `requestFrom(addr, qty, stop, rxBuf, cb, user)`	NEW: Non-blocking with callback
External RX buffer	❌ N/A	✅ `requestFrom(rxBuffer=ptr)`	NEW: Zero-copy async receives
Buffer management	❌ N/A	✅ `setRxBuffer/setTxBuffer/...`	NEW: External buffer control
10-bit addressing	❌ N/A	✅ `begin(addr, ..., enable10Bit)`	NEW: Enhanced addressing mode
Speed parameter	❌ N/A	✅ `begin(..., speed)`	NEW: Direct speed control
Write zero-copy	❌ N/A	✅ `write(data, qty, setExternal=true)`	NEW: External buffer for TX
Default callbacks	N/A	✅ Both optional	Seamless: sync when nullptr, async when provided

Wire Design Pattern Notes

Wire uses a multi-stage transaction builder pattern:

beginTransmission(address) - Start building
write(...) - Add data to staging buffer (loader transaction)
endTransmission(callback) - Execute the built transaction (sync or async)

Or for reads:

requestFrom(address, quantity, callback) - Execute read transaction directly

This pattern influenced the unified API approach for UART and SPI, but those interfaces use single-call operations rather than multi-stage building.

Key Enhancement: The sercom-async-dma branch adds async callback support to the Wire API while maintaining full backward compatibility with the synchronous blocking behavior. When callbacks are nullptr (default), behavior is identical to master branch.

UART API Changes

Master Branch (Original)

class Uart : public HardwareSerial {
  public:
    int read();
    size_t write(const uint8_t data);
    // Inherits: write(str) from Print
};

sercom-async-dma Branch (New)

class Uart : public HardwareSerial {
  public:
    int read();
    
    // NEW: Buffer-based async/sync read with optional callback
    size_t read(uint8_t* buffer, size_t size,
                void (*onComplete)(void* user, int status) = nullptr,
                void* user = nullptr);
    
    size_t write(const uint8_t data);
    
    // NEW: Buffer-based async/sync write with optional callback
    // If callback is nullptr, blocks (sync). Otherwise enqueues and returns (async).
    size_t write(const uint8_t* buffer, size_t size,
                 void (*onComplete)(void* user, int status) = nullptr,
                 void* user = nullptr);
    
    // Inherits: write(str) from Print
};

UART API Summary

Feature	Master	sercom-async-dma	Notes
Single-byte read	✅ `int read()`	✅ (unchanged)	Traditional API preserved
Single-byte write	✅ `size_t write(uint8_t)`	✅ (unchanged)	Traditional API preserved
Buffer read (sync)	❌ N/A	✅ `read(buf, size)`	NEW: Ring buffer read
Buffer read (async)	❌ N/A	✅ `read(buf, size, callback)`	NEW: DMA-accelerated async read
Buffer write (sync)	❌ N/A	✅ `write(buf, size)`	NEW: DMA or byte-by-byte write
Buffer write (async)	❌ N/A	✅ `write(buf, size, callback)`	NEW: DMA-accelerated async write
Default callbacks	N/A	✅ Both optional	Seamless: sync when nullptr, async when provided

API Strategy: Single unified method with optional callback parameter (like Wire)

SPI API Changes

Master Branch (Original)

class SPIClass {
  public:
    byte transfer(uint8_t data);
    uint16_t transfer16(uint16_t data);
    void transfer(void *buf, size_t count);
    
    // Blocking only, no async support
    void transfer(const void* txbuf, void* rxbuf, size_t count, 
                  bool block = true);
};

sercom-async-dma Branch (New)

class SPIClass {
  public:
    byte transfer(uint8_t data);
    uint16_t transfer16(uint16_t data);
    void transfer(void *buf, size_t count);
    
    // MODIFIED: Added async callback parameters
    void transfer(const void* txbuf, void* rxbuf, size_t count,
                  bool block = true,
                  void (*onComplete)(void* user, int status) = nullptr,
                  void* user = nullptr);
    
    void waitForTransfer(void);
    bool isBusy(void);
};

SPI API Summary

Feature	Master	sercom-async-dma	Notes
Single-byte transfer	✅	✅ (unchanged)	Traditional API preserved
16-bit transfer	✅	✅ (unchanged)	Traditional API preserved
Buffer transfer (blocking)	✅ `void transfer(void*)`	✅ (unchanged)	For small transfers
Dual-buffer transfer (sync)	✅ `transfer(tx, rx, count, true)`	✅ (unchanged)	Explicit blocking
Dual-buffer transfer (async)	❌ N/A	✅ `transfer(tx, rx, count, true, callback)`	NEW: Async callback parameter
Default callbacks	N/A	✅ Optional (`nullptr`)	Sync-only by default for compatibility

API Strategy: Extended existing method signature with optional callback parameters

Wire API (For Reference)

Wire already had async/DMA in master, but documentation for pattern:

class TwoWire {
  public:
    uint8_t sendTransmission(void (*onComplete)(...) = nullptr, ...);      // Sync or async
    uint8_t requestFrom(uint8_t address, size_t quantity,
                        uint8_t* rxBuffer = nullptr,
                        void (*onComplete)(...) = nullptr, ...);           // Sync or async
};

Cross-Interface API Patterns

Design Consistency

Pattern	Wire	SPI	UART
Callback parameter	✅ Optional (default nullptr)	✅ Optional (default nullptr)	✅ Optional (default nullptr)
Sync/Async duality	✅ Single method handles both	✅ Single method handles both	✅ Single method handles both
Blocks when callback is nullptr	✅	✅	✅
Transaction pool	✅ (8-txn)	✅ (8-txn)	✅ (8-txn)
DMA acceleration	✅	✅	✅
Fallback (non-DMA)	✅ Byte-by-byte	✅ Byte-by-byte	✅ Byte-by-byte
User API changes	Minimal	Extended (added callback)	Extended (added callback)
Backwards compat	✅ 100%	✅ 100% (default params)	✅ 100% (new overloads)

Async Pattern (All Three Interfaces)

// Synchronous: blocks until complete (no callback)
interface.method(data, size);

// Asynchronous: enqueues and returns immediately (with callback)
interface.method(data, size, [](void* user, int status) {
    // Transfer complete
}, userData);

Note: For async calls, any user-provided buffers must remain valid until the completion callback fires.

Coverage Analysis

UART Coverage

Before (Master):

✅ HardwareSerial compatibility (single-byte only)
❌ No efficient buffer operations
❌ No async support
❌ No DMA acceleration

After (sercom-async-dma):

✅ HardwareSerial compatibility (preserved)
✅ Efficient buffer operations (both directions)
✅ Async support via callbacks
✅ DMA acceleration when enabled
✅ Automatic fallback to byte-by-byte when DMA unavailable

SPI Coverage

Before (Master):

✅ Single-byte transfers
✅ 16-bit transfers
✅ Buffer transfers (blocking)
✅ Dual-buffer transfers (blocking)
❌ No async callback support
❌ Limited transaction scheduling

After (sercom-async-dma):

✅ All prior functionality preserved
✅ Async callback support (new optional parameters)
✅ Transaction pool for queuing multiple operations
✅ DMA acceleration
✅ Explicit waitForTransfer() check for non-blocking code paths

Fingerprint (Method Signature) Differences

UART: New Overloads Added

// Master: NO OVERLOAD
// sercom-async-dma: NEW
size_t read(uint8_t* buffer, size_t size,
            void (*onComplete)(void* user, int status) = nullptr,
            void* user = nullptr);

// Master: NO OVERLOAD
// sercom-async-dma: NEW
size_t write(const uint8_t* buffer, size_t size,
             void (*onComplete)(void* user, int status) = nullptr,
             void* user = nullptr);

SPI: Existing Signature Extended

// Master
void transfer(const void* txbuf, void* rxbuf, size_t count, bool block = true);

// sercom-async-dma: Added optional callback parameters (backward compatible)
void transfer(const void* txbuf, void* rxbuf, size_t count,
              bool block = true,
              void (*onComplete)(void* user, int status) = nullptr,  // NEW (optional)
              void* user = nullptr);                                  // NEW (optional)

Default Parameter Behavior

UART New Methods (Defaults)

read(buffer, size);                              // Defaults: sync (no callback)
read(buffer, size, nullptr, nullptr);            // Explicit sync
read(buffer, size, myCallback, userData);        // Async

write(buffer, size);                             // Defaults: sync (no callback)
write(buffer, size, nullptr, nullptr);           // Explicit sync
write(buffer, size, myCallback, userData);       // Async

SPI Extended Method (Defaults)

transfer(tx, rx, count);                         // Defaults: sync (no callback)
transfer(tx, rx, count, true);                   // Explicit sync blocking
transfer(tx, rx, count, true, nullptr, nullptr); // Explicit sync
transfer(tx, rx, count, true, myCallback, data); // Async

Implementation Transparency

Aspect	Master	sercom-async-dma	User Awareness
Transaction pooling	❌ Internal only	✅ Internal only	❌ None (transparent)
DMA vs fallback	❌ N/A	✅ Automatic	❌ None (transparent)
USE_ZERODMA define	N/A	✅ Internal only	❌ None (transparent)
Interrupt management	✅ Automatic	✅ Automatic	❌ None (transparent)

Test Coverage

UART Functional Tests (NEW)

✅ SyncWrite_BasicOperation - Single buffer write (sync)
✅ AsyncWrite_CallbackCompletion - Async write with callback
✅ TransactionPool_MultipleQueued - 3+ simultaneous async operations
✅ RingBuffer_Availability - Buffer space tracking
✅ Configuration_Enable - Hardware initialization

SPI Hardware Tests (NEW)

✅ ReadGCONF_Sync - Single register read (sync)
✅ ReadGSTAT_Sync - Status register
✅ ReadIFCNT_Sync - Interface counter (proves queuing work)
✅ ReadXACTUAL_Async - Single async read with callback
✅ WriteThenReadChopconf_Sync - Register write/read cycle
✅ MultipleAsyncTransfersQueued - 3+ queued async operations

Master Branch

No async/DMA tests (feature didn't exist)

Summary of Changes

What's New

UART:
- ✅ New async/DMA read capability via read(buffer, size, callback, user)
- ✅ New async/DMA write capability via write(buffer, size, callback, user)
- ✅ Internal transaction pool (8 entries)
- ✅ Seamless DMA/fallback switching
SPI:
- ✅ New async callback support via extended transfer() signature
- ✅ Internal transaction pool (8 entries)
- ✅ Seamless DMA/fallback switching
- ✅ waitForTransfer() and isBusy() for non-blocking patterns
Both:
- ✅ 100% backward compatible (old API unchanged)
- ✅ Unified async pattern across Wire, SPI, UART
- ✅ Transparent DMA acceleration

What Changed in Existing API

✅ SPI transfer() signature extended with optional parameters
✅ All defaults preserve synchronous blocking behavior
✅ Zero breaking changes

What Stayed the Same

✅ Single-byte operations (UART read/write, SPI transfer)
✅ HardwareSerial inheritance (UART)
✅ SPISetting class and configuration
✅ Transaction-based API (Wire, endTransaction/beginTransaction)
✅ Interrupt handling (automatic)

Migration Guide: Master → sercom-async-dma

UART: No changes required

// Master code works as-is
Serial.write(data);
int b = Serial.read();

Opt-in to new async features

// NEW: Async write
uint8_t buffer[] = {1, 2, 3, 4};
Serial.write(buffer, 4, [](void* user, int status) {
    // Transfer complete
}, nullptr);

// NEW: Async read
Serial.read(buffer, 4, [](void* user, int status) {
    // Data received
}, nullptr);

SPI: No changes required

// Master code works as-is
SPI.transfer(tx, rx, count, true);

Opt-in to new async features

// NEW: Async transfer
SPI.transfer(tx, rx, count, true, [](void* user, int status) {
    // Transfer complete
}, nullptr);

Verdict

✅ API design is clean and consistent:

UART and SPI follow the same unified pattern as Wire
Optional callback parameter = automatic sync/async selection
100% backward compatible
Zero learning curve for existing code
Async capability is seamlessly available without cluttering the API

Update 17 Feb 2026: added links to repositories for SerialRTT and DebugUtils

…ol configuration

…in a multi-master configuration

…erving legacy behavior.

…added stopTransmissionWIRE to allow sync closeout, handle errors and continue processing the transaction queue

…g ISR called APIs

…onsistently

…or pin assignment validation

Upstream commit 289a272 added ERROR flag clearing for synchronous blocking I2C operations, but this branch uses ISR-driven async architecture where errors are handled and cleared immediately in interrupt context. The upstream fix doesn't apply to the rewritten async code.

- Fix misleading indentation in retry logic (lines 847, 857) - Remove ambiguous overload for Wire.begin() with integer literals (uint16_t version now requires explicit enableGeneralCall parameter) - Remove unused variable in SPI.cpp - Remove redundant unsigned < 0 check in setPending()

- Add __attribute__((weak)) to all SPI interrupt handlers (SERCOM4, SPI1, etc) This allows variants to override them when SERCOM is used for other peripherals (e.g., MKR variants use SERCOM4 for Serial2/UART) - Explicitly cast slave addresses to uint8_t in Wire examples to avoid any potential overload resolution issues on different compiler versions

crabel99 added 22 commits January 27, 2026 19:38

define sercom transaction structure for enqueueing async transactions.

3f45eb5

provide unified structure for maintaining and accessing sercom protoc…

de24356

…ol configuration

add support for mux pin deconfliction during development.

2c9e540

integrate needed dma sercom structure into the SERCOM class

86ee1c4

refactored initMaster/SlaveWIRE() to support rapid swapping of roles …

82b1d3a

…in a multi-master configuration

generalize RingBuffer to support any type not just uint8_t while pres…

b0d39fd

…erving legacy behavior.

refactored stopTransmissionWIRE to support DMA and async operations, …

3586cf6

…added stopTransmissionWIRE to allow sync closeout, handle errors and continue processing the transaction queue

add 10-bit address support for client operations

7a353b0

finish implementing wire async and dma callback structure and inlinin…

b0fbebc

…g ISR called APIs

add async and automatic dma support for client mode operations.

a956137

refactor SPI to use SERCOM dma implementation

6c58fd5

stage more UART DMA structure

10b86e3

unify structure between different sercoms to mirror each other more c…

6e6d303

…onsistently

get sercom's wire protocol working in master mode

18a3924

clean up SPI

66c1ff7

finish refactor of Wire to fully use async SERCOM

430e8bf

master wire fully tested sync/async

51e0dd5

test SPI sync and async operations

d5d0430

high level testing no hardware testing done on UART

6bb67bc

refactor to use async sercom api's

9370d6a

samd datasheet multiplexing tables as csv

c4bc1bd

script to generate wire sercom specific pin assignments can be used f…

f4fc47a

…or pin assignment validation

crabel99 mentioned this pull request Feb 17, 2026

Integrated support for DMA into SERCOM for SPI/UART/Wire #382

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crabel99 added 3 commits February 16, 2026 23:26

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SERCOM async/DMA for Wire, SPI, and UART#385

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SERCOM Async/DMA API Comparison: sercom-async-dma vs Master

Executive Summary

Motivation

Design Intent

Philosophy

Hardware Testing Status

✅ Tested Configurations

⚠️ Untested Configurations

Recommended Pre-Merge Validation

Known Limitations & Future Development

API Change Summary

Detailed API Comparison

Wire API Changes

Master Branch (Original)

sercom-async-dma Branch (Enhanced)

Wire API Summary

Wire Design Pattern Notes

UART API Changes

Master Branch (Original)

sercom-async-dma Branch (New)

UART API Summary

SPI API Changes

Master Branch (Original)

sercom-async-dma Branch (New)

SPI API Summary

Wire API (For Reference)

Cross-Interface API Patterns

Design Consistency

Async Pattern (All Three Interfaces)

Coverage Analysis

UART Coverage

SPI Coverage

Fingerprint (Method Signature) Differences

UART: New Overloads Added

SPI: Existing Signature Extended

Default Parameter Behavior

UART New Methods (Defaults)

SPI Extended Method (Defaults)

Implementation Transparency

Test Coverage

UART Functional Tests (NEW)

SPI Hardware Tests (NEW)

Master Branch

Summary of Changes

What's New

What Changed in Existing API

What Stayed the Same

Migration Guide: Master → sercom-async-dma

UART: No changes required

Opt-in to new async features

SPI: No changes required

Opt-in to new async features

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Comments

crabel99 commented Feb 17, 2026 •

edited

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