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Add a new set of RISC-V extensions (goal is RVA23 profile)#344

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Add a new set of RISC-V extensions (goal is RVA23 profile)#344
edubart wants to merge 10 commits intomainfrom
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@edubart edubart commented Dec 4, 2025 •
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This PR adds support for a bunch of new RISC-V extensions, the goal is to slowly increase support for mandatory RISC-V extensions required by the RVA23 profile.

New instructions added

  • B - Bit manipulation
    • Zba - Address generation
      • ADD.UW - Add unsigned word
      • SH1ADD - Shift left by 1 and add
      • SH1ADD.UW - Shift unsigned word left by 1 and add
      • SH2ADD - Shift left by 2 and add
      • SH2ADD.UW - Shift unsigned word left by 2 and add
      • SH3ADD - Shift left by 3 and add
      • SH3ADD.UW - Shift unsigned word left by 3 and add
      • SLLI.UW - Shift-left unsigned word (Immediate)
    • Zbb - Basic bit-manipulation
      • ANDN - AND with inverted operand
      • ORN - OR with inverted operand
      • XNOR - Exclusive NOR
      • CLZ - Count leading zero bits
      • CLZW - Count leading zero bits in word
      • CTZ - Count trailing zero bits
      • CTZW - Count trailing zero bits in word
      • CPOP - Count set bits
      • CPOPW - Count set bits in word
      • MAX - Signed Maximum
      • MAXU - Unsigned maximum
      • MIN - Signed Minimum
      • MINU - Unsigned minimum
      • SEXT.B - Sign-extend byte
      • SEXT.H - Sign-extend halfword
      • ZEXT.H - Zero-extend halfword
      • ROL - Rotate left (Register)
      • ROLW - Rotate Left Word (Register)
      • ROR - Rotate right (Register)
      • RORI - Rotate right (Immediate)
      • RORIW - Rotate right Word (Immediate)
      • RORW - Rotate right Word (Register)
      • ORC.B - Bitwise OR-Combine, byte granule
      • REV8 - Byte-reverse register
    • Zbs - Single-Bit Manipulation
      • BCLR - Single-Bit Clear (Register)
      • BCLRI - Single-Bit Clear (Immediate)
      • BEXT - Single-Bit Extract (Register)
      • BEXTI - Single-Bit Extract (Immediate)
      • BINV - Single-Bit Invert (Register)
      • BINVI - Single-Bit Invert (Immediate)
      • BSET - Single-Bit Set (Register)
      • BSETI - Single-Bit Set (Immediate)
  • Zbc - Carryless multiplication
    • CLMUL - Carry-less multiply (low-part)
    • CLMULH - Carry-less multiply (high-part)
    • CLMULR - Carry-less multiply (reversed)
  • Zfhmin - Half-precision floating-point minimal
    • FLH
    • FSH
    • FMV.X.H
    • FMV.H.X
    • FCVT.S.H
    • FCVT.H.S
    • FCVT.D.H
    • FCVT.H.D
  • Zfh - Half-precision floating-point
    • FMADD.H
    • FMSUB.H
    • FNMSUB.H
    • FNMADD.H
    • FADD.H
    • FSUB.H
    • FMUL.H
    • FDIV.H
    • FSQRT.H
    • FSGNJ.H
    • FSGNJN.H
    • FSGNJX.H
    • FMIN.H
    • FMAX.H
    • FEQ.H
    • FLT.H
    • FLE.H
    • FCLASS.H
    • FCVT.W.H
    • FCVT.WU.H
    • FCVT.H.W
    • FCVT.H.WU
    • FCVT.L.H
    • FCVT.LU.H
    • FCVT.H.L
    • FCVT.H.LU
  • Zicond - Integer conditional operations
    • CZERO.EQZ - Conditional zero, if condition is equal to zero
    • CZERO.NEZ - Conditional zero, if condition is nonzero
  • Zcb - Additional compressed instructions
    • C.LBU - Load unsigned byte, 16-bit encoding
    • C.LHU - Load unsigned halfword, 16-bit encoding
    • C.LH - Load signed halfword, 16-bit encoding
    • C.SB - Store byte, 16-bit encoding
    • C.SH - Store halfword, 16-bit encoding
    • C.ZEXT.B - Zero extend byte, 16-bit encoding
    • C.SEXT.B - Sign extend byte, 16-bit encodacng
    • C.ZEXT.H - Zero extend halfword, 16-bit encoding
    • C.SEXT.H - Sign extend halfword, 16-bit encoding
    • C.ZEXT.W - Zero extend word, 16-bit encoding
    • C.NOT - Bitwise not, 16-bit encoding
    • C.MUL - Multiply, 16-bit encoding

Planned for this PR but not implemented yet

  • Zfa - Additional floating-point instructions
    • FLI.H
    • FLI.S
    • FLI.D
    • FMINM.H
    • FMINM.S
    • FMINM.D
    • FMAXM.H
    • FMAXM.S
    • FMAXM.D
    • FROUND.H
    • FROUND.S
    • FROUND.D
    • FROUNDNX.H
    • FROUNDNX.S
    • FROUNDNX.D
    • FLEQ.H
    • FLEQ.S
    • FLEQ.D
    • FLTQ.H
    • FLTQ.S
    • FLTQ.D
    • FCVTMOD.W.D
  • Zimop - May-be-operations
    • MOP.R.n
    • MOP.PR.n
  • Zcmop - Compressed may-be-operations
    • C.MOP.n
  • Zawrs - Wait-on-Reservation-Set
    • WRS.NTO
    • WRS.STO
  • Zicbom
    • CBO.CLEAN - Cache Block Clean
    • CBO.FLUSH - Cache Block Flush
  • Zicboz
    • CBO.INVAL - Cache Block Invalidate
    • CBO.ZERO - Cache Block Zero
  • Zicbop
    • PREFETCH.I - Prefetch Instruction
    • PREFETCH.R - Prefetch Read
    • PREFETCH.W - Prefetch Write

@edubart edubart self-assigned this Dec 4, 2025
@edubart edubart added the enhancement New feature or request label Dec 4, 2025
@edubart edubart moved this from Todo to In Progress in Machine Unit Dec 4, 2025
@edubart edubart marked this pull request as draft December 4, 2025 20:26
@edubart edubart force-pushed the feature/rva23-set1 branch 3 times, most recently from 2cc330c to a02b3d6 Compare December 5, 2025 22:40
@edubart edubart force-pushed the feature/rva23-set1 branch 3 times, most recently from 232bca2 to b660490 Compare December 9, 2025 01:02
@edubart edubart force-pushed the feature/rva23-set1 branch from b660490 to 6ecd676 Compare December 9, 2025 21:36
@edubart edubart moved this from In Progress to On Hold in Machine Unit Apr 9, 2026
@edubart edubart added this to the v0.21.0 milestone Apr 14, 2026
diegonehab added a commit that referenced this pull request Apr 17, 2026
@diegonehab
feat: decode RISC-V Zcb compressed extension
251d819 
Adds decoding for C.LBU, C.LHU, C.LH, C.SB, C.SH, C.ZEXT.B,
C.SEXT.B, C.ZEXT.H, C.SEXT.H, C.ZEXT.W, C.NOT, C.MUL.

Necessary because gcc 14 emits Zcb encodings (e.g. 0x8000 = c.lbu)
for the RISC-V kernel build, which previously raised illegal-insn
and caused an infinite trap loop.

Ported from Eduardo's work on PR #344 (only the Zcb commit).
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Status: On Hold

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