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Peter Chen edited this page Jan 12, 2026 · 13 revisions

Welcome to the CIX Linux Kernel Upstream wiki!

This wiki page is used for CIX SoCs mainline Linux kernel status update.

Upstream Status

CIX P1 (Sky1) SoC
Component Status Link
Basic DT v6.17-rc1 https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
MAILBOX/UART/Clock v6.17-rc1 https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
I2C & I3C v6.18-rc1 https://lore.kernel.org/all/20250903084713.3221907-1-jun.guo@cixtech.com/
SPI v6.19-rc1 https://lore.kernel.org/r/20250919013118.853078-1-jun.guo@cixtech.com/
Pinctrl v6.19-rc1 https://lore.kernel.org/all/20251021070410.3585997-1-gary.yang@cixtech.com/
PCIe v6.19-rc1 https://lore.kernel.org/linux-pci/20251020042857.706786-1-hans.zhang@cixtech.com/
HDA v6.19-rc1 v6
Reset Reviewing v3
DMA Reviewing https://lkml.org/lkml/2025/11/17/69
GPIO Planning  
Power Domain Planning  
USB Planning  
USB/DP Combo PHY Planning  
CPU Idle Planning  
CPU DVFS Planning  
I2S Planning  
DPU Planning  
DP Planning  
GPU Planning  
VPU Planning  
NPU Planning  
ISP Planning  
CSI Planning  
RPMSG Planning  
GMAC Planning  
System PM Planning  
CIX P1 (Sky1) SoC based boards
Component Status Link
Radxa Orion O6 v6.17-rc1 https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
Xunlong Orangepi 6 plus v6.20-rc1 v4

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