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Achievements

Achievement: QuickdrawAchievement: YOLOAchievement: Pull Shark

Achievements

Achievement: QuickdrawAchievement: YOLOAchievement: Pull Shark

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@REBECCA-CHIP

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jimaandro/README.md

Hi 👋, I'm Dimitris

A passionate hardware design engineer with a background in FPGA design, SoC integration, and processor architectures. I hold an Integrated Master’s degree in Electrical and Computer Engineering from Aristotle University of Thessaloniki (AUTH) and am currently pursuing a Master’s in Computer Science at the University of Crete.

  • 🔭 I’m currently working on the REBECCA Project (Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AI).
  • 🌱 My current research focuses on Fully Homomorphic Encryption (FHE) accelerators, which is also the subject of my master’s thesis.

Connect with me:

dimitris-andronikou

Languages and Tools:

Verilog SystemVerilog Xilinx Vivado Synopsys VCS Cadence Genus

Verilator c cplusplus java git docker kubernetes linux



GitHub Streak

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  1. JTAG_TO_AXI JTAG_TO_AXI Public

    These scripts are used in a Vivado project, to implement jtag to axi transactions.

    Tcl 2

  2. MIPS_processor MIPS_processor Public

    This is a university project. It is an implementation ant testing of MIPS processor in verilog.

    C 1

  3. ASIC ASIC Public

    Tcl 1

  4. generic_flP_alu generic_flP_alu Public

    Tcl 2

  5. e-left/advanced_computer_architecture_lab2 e-left/advanced_computer_architecture_lab2 Public

    Lab reports, along with code samples and statistics for the Advanced Computer Architecture course

    Shell

  6. e-left/advanced_computer_architecture_lab1 e-left/advanced_computer_architecture_lab1 Public

    Lab reports, along with code samples and statistics for the Advanced Computer Architecture course

    C