[gpio,dv] Re-add block-level DV for GPIO IP

hw/top_chip/dv/mocha_sim_cfgs.hjson

@@ -27,7 +27,7 @@
     "{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson",
     "{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/i2c_sim_cfg.hjson",
-    "{proj_root}/hw/top_chip/tmp_sim_cfg/gpio_sim_cfg.hjson",
+    "{proj_root}/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/rom_ctrl_32kB_sim_cfg.hjson",
     "{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson",
 

hw/top_chip/ip_autogen/gpio/data/gpio_testplan.hjson

@@ -3,11 +3,11 @@
 // SPDX-License-Identifier: Apache-2.0
 {
   name: "gpio"
-  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                      "gpio_sec_cm_testplan.hjson"]
   testpoints: [
     {

hw/top_chip/ip_autogen/gpio/dv/env/gpio_scoreboard.sv

@@ -358,44 +358,29 @@ class gpio_scoreboard extends cip_base_scoreboard #(.CFG_T (gpio_env_cfg),
     end
   endtask : monitor_gpio_interrupt_pins
 
-  virtual task update_gpio_straps_regs(logic [NUM_GPIOS-1:0] gpio_i_sampled);
-    // Update data_in and data_in_valid ral register value based on result of input
-    `DV_CHECK_FATAL(ral.hw_straps_data_in.predict(.value(gpio_i_sampled),
-                                                  .kind(UVM_PREDICT_READ)));
-    `DV_CHECK_FATAL(ral.hw_straps_data_in_valid.predict(.value('b1),
-                                                        .kind(UVM_PREDICT_READ)));
-  endtask : update_gpio_straps_regs
-
   // Task: monitor_gpio_straps
   // The task monitors the gpio straps enable signal
   // and checks the straps output signal after the first strap trigger
   virtual task monitor_gpio_straps();
-    logic [NUM_GPIOS-1:0] gpio_i_sampled;
     forever begin : monitor_gpio_straps
-      // Wait for going out of reset operation.
+      // Wait to leave reset
       wait(!cfg.under_reset);
-      // Wait until the strap_en input be triggered
-      // if a reset comes in the middle, step-out of the loop.
-      while (!cfg.straps_vif_inst.tb_port.strap_en) begin
-        cfg.clk_rst_vif.wait_clks_or_rst(1);
-        if (cfg.under_reset) break;
-      end
-      // Step out to the next iteration if a reset happens.
-      if (cfg.under_reset) continue;
-      // Get the gpio_i input data from the pins interface.
-      gpio_i_sampled = cfg.gpio_vif.pins;
-      // Wait for one clock cycle to update the register model.
-      cfg.clk_rst_vif.wait_clks_or_rst(1);
-      // Step out from the loop if a reset comes.
+
+      // Now wait until strap_en goes high, dropping out if we go back into reset
+      fork : isolation_fork begin
+        fork
+          wait(cfg.straps_vif_inst.tb_port.strap_en);
+          wait(cfg.under_reset);
+        join_any
+        disable fork;
+      end join
       if (cfg.under_reset) continue;
-      // Update the register model.
-      update_gpio_straps_regs(gpio_i_sampled);
-
-      // Checker: Compare actual values of gpio pins with straps register.
-      // Check the register hw_straps_data_in against gpio_i pins
-      `DV_CHECK_CASE_EQ(gpio_i_sampled, cfg.straps_vif_inst.tb_port.sampled_straps.data)
-      // Check the register hw_straps_data_in_valid
-      `DV_CHECK_CASE_EQ('b1, cfg.straps_vif_inst.tb_port.sampled_straps.valid)
+
+      // Sample the pins, storing the value and a validity bit in the register model.
+      if (!ral.hw_straps_data_in.predict(.value(cfg.gpio_vif.pins), .kind(UVM_PREDICT_DIRECT)))
+        `uvm_fatal(get_full_name(), "Failed to update HW_STRAPS_DATA_IN prediction.")
+      if (!ral.hw_straps_data_in_valid.predict(.value(1), .kind(UVM_PREDICT_DIRECT)))
+        `uvm_fatal(get_full_name(), "Failed to update HW_STRAPS_DATA_IN_VALID prediction.")
 
       // Wait for the next reset, if it happens.
       wait(cfg.under_reset);

hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson

@@ -12,7 +12,7 @@
   tb: tb
 
   // Simulator used to sign off this block
-  tool: vcs
+  tool: xcelium
 
   // Fusesoc core file used for building the file list.
   fusesoc_core: lowrisc:mocha_dv:gpio_sim:0.1
@@ -26,14 +26,14 @@
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson"]
 
   // Add additional tops for simulation.
   sim_tops: ["gpio_bind", "sec_cm_prim_onehot_check_bind"]

hw/top_chip/ip_autogen/pwrmgr/data/pwrmgr.hjson

@@ -160,9 +160,9 @@
       package: "lc_ctrl_pkg",
     },
 
-    { struct:  "pwr_flash",
+    { struct:  "pwr_nvm",
       type:    "uni",
-      name:    "pwr_flash",
+      name:    "pwr_nvm",
       act:     "rcv",
       package: "pwrmgr_pkg",
     },
@@ -729,7 +729,7 @@
           name: "ABORT",
           desc: '''
             The abort wakeup reason indicates that despite setting a WFI and providing a low power
-            hint, an active flash / lifecycle / otp transaction was ongoing when the power controller
+            hint, an active NVM / lifecycle / otp transaction was ongoing when the power controller
             attempted to initiate low power entry.
 
             The power manager detects this condition, halts low power entry and reports as a wakeup reason

hw/top_chip/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson

@@ -106,14 +106,14 @@
             Low power transitions can be aborted in two cases:
             - The processor gets an interrupt soon after a low power entry is
               triggered.
-            - OTP, LC, or FLASH are not idle.
+            - OTP, LC, or NVM are not idle.
             This test aborts low power transitions, and disables any wakeups,
             so the test would timeout if low power was entered.
 
             **Stimulus**:
             - Bring pwrmgr to low power.
             - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`,
-              `otp_idle`, or `flash_idle` inputs off.
+              `otp_idle`, or `nvm_idle` inputs off.
             - Disable all wakeup enables.
             - Randomly set `wakeup_info_capture_dis` CSR.
 

hw/top_chip/ip_autogen/pwrmgr/dv/README.md

@@ -112,7 +112,7 @@ The test sequences besides the base are as follows:
 * `pwrmgr_wakeup_vseq` checks the transitions to low power and the wakeup settings.
   It randomizes wakeup inputs, wakeup enables, the wakeup info capture enable, and the interrupt enable.
 * `pwrmgr_aborted_low_power_vseq` creates scenarios that lead to aborting a low power transition.
-  The abort can be due to the processor waking up very soon, or otp, lc, or flash being busy.
+  The abort can be due to the processor waking up very soon, or otp, lc, or nvm being busy.
 * `pwrmgr_reset_vseq` checks the pwrmgr response to conditional resets and reset enables, and unconditional escalation and main power glitch resets.
 * `pwrmgr_wakeup_reset_vseq` aligns reset and wakeup from low power.
 * `pwrmgr_lowpower_wakeup_race_vseq` aligns a wakeup event coming in proximity to low power entry.
@@ -210,8 +210,8 @@ See also the test plan for specific ways these are driven to trigger different t
 ##### LC
 The pins connecting to LC behave pretty much the same way as those to OTP.
 
-##### FLASH
-- Input `flash_idle` is handled much like `lc_idle` and `otp_idle`.
+##### NVM
+- Input `nvm_idle` is handled much like `lc_idle` and `otp_idle`.
 
 ##### CPU
 - Input `core_sleeping` is driven by sequences.

hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv

@@ -36,7 +36,7 @@ interface pwrmgr_if (
   lc_ctrl_pkg::pwr_lc_req_t                                        pwr_lc_req;
   lc_ctrl_pkg::pwr_lc_rsp_t                                        pwr_lc_rsp;
 
-  pwrmgr_pkg::pwr_flash_t                                          pwr_flash;
+  pwrmgr_pkg::pwr_nvm_t                                            pwr_nvm;
 
   pwrmgr_pkg::pwrmgr_cpu_t                                         cpu_i;
   rv_core_ibex_pkg::cpu_pwrmgr_t                                   pwr_cpu;
@@ -152,8 +152,8 @@ interface pwrmgr_if (
     pwr_lc_rsp.lc_idle = value;
   endfunction
 
-  function automatic void update_flash_idle(logic value);
-    pwr_flash.flash_idle = value;
+  function automatic void update_nvm_idle(logic value);
+    pwr_nvm.nvm_idle = value;
   endfunction
 
   function automatic void update_cpu_sleeping(logic value);
@@ -202,7 +202,7 @@ interface pwrmgr_if (
     pwr_clk_rsp = '{default: '0};
     pwr_otp_rsp = '{default: '0};
     pwr_lc_rsp = '{default: '0};
-    pwr_flash = '{default: '0};
+    pwr_nvm = '{default: '0};
     pwr_cpu = rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT;
     wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT;
     rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT;

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv

@@ -21,13 +21,13 @@ class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq;
     };
   }
 
-  rand bit flash_idle;
+  rand bit nvm_idle;
   rand bit lc_idle;
   rand bit otp_idle;
 
   constraint idle_c {
-    solve cpu_interrupt before flash_idle, lc_idle, otp_idle;
-    if (!cpu_interrupt) {(flash_idle && lc_idle && otp_idle) == 1'b0;}
+    solve cpu_interrupt before nvm_idle, lc_idle, otp_idle;
+    if (!cpu_interrupt) {(nvm_idle && lc_idle && otp_idle) == 1'b0;}
   }
 
   constraint wakeups_c {wakeups != 0;}
@@ -84,12 +84,12 @@ class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq;
             cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
           end else begin
             `uvm_info(`gfn, $sformatf(
-                      "Expecting an abort (0x80): fi=%b, li=%b, oi=%b",
-                      flash_idle,
+                      "Expecting an abort (0x80): nvm_idle=%b, lc_idle=%b, otp_idle=%b",
+                      nvm_idle,
                       lc_idle,
                       otp_idle
                       ), UVM_MEDIUM)
-            set_nvms_idle(flash_idle, lc_idle, otp_idle);
+            set_nvms_idle(nvm_idle, lc_idle, otp_idle);
           end
         end
       join

hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv

@@ -493,7 +493,7 @@ class pwrmgr_base_vseq extends cip_base_vseq #(
 
   local task wait_for_abort();
     `DV_WAIT(
-        !cfg.pwrmgr_vif.pwr_flash.flash_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle ||
+        !cfg.pwrmgr_vif.pwr_nvm.nvm_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle ||
           !cfg.pwrmgr_vif.pwr_lc_rsp.lc_idle)
     exp_intr = 1'b1;
     `uvm_info(`gfn, "wait_for_abort succeeds", UVM_MEDIUM)
@@ -562,11 +562,11 @@ class pwrmgr_base_vseq extends cip_base_vseq #(
   // This enables the fast fsm to transition to low power when all nvms are idle after the
   // transition is enabled by software and cpu WFI. When not all are idle the transition is
   // aborted.
-  virtual task set_nvms_idle(logic flash_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1);
+  virtual task set_nvms_idle(logic nvm_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1);
     `uvm_info(`gfn, $sformatf(
-              "Setting nvms idle: flash=%b, lc=%b, otp=%b", flash_idle, lc_idle, otp_idle),
+              "Setting nvms idle: nvm=%b, lc=%b, otp=%b", nvm_idle, lc_idle, otp_idle),
               UVM_MEDIUM)
-    cfg.pwrmgr_vif.update_flash_idle(flash_idle);
+    cfg.pwrmgr_vif.update_nvm_idle(nvm_idle);
     cfg.pwrmgr_vif.update_lc_idle(lc_idle);
     cfg.pwrmgr_vif.update_otp_idle(otp_idle);
   endtask

hw/top_chip/ip_autogen/pwrmgr/dv/tb.sv

@@ -90,7 +90,7 @@ module tb;
     .pwr_lc_i(pwrmgr_if.pwr_lc_rsp),
     .pwr_lc_o(pwrmgr_if.pwr_lc_req),
 
-    .pwr_flash_i(pwrmgr_if.pwr_flash),
+    .pwr_nvm_i(pwrmgr_if.pwr_nvm),
     .pwr_cpu_i  (pwrmgr_if.pwr_cpu),
 
     .fetch_en_o(pwrmgr_if.fetch_en),

hw/top_chip/ip_autogen/pwrmgr/rtl/pwrmgr.sv

@@ -56,8 +56,8 @@ module pwrmgr
   input  lc_ctrl_pkg::pwr_lc_rsp_t pwr_lc_i,
   output lc_ctrl_pkg::pwr_lc_req_t pwr_lc_o,
 
-  // flash interface
-  input  pwr_flash_t pwr_flash_i,
+  // NVM interface
+  input  pwr_nvm_t pwr_nvm_i,
 
   // processor interface
   input  rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu_i,
@@ -269,7 +269,7 @@ module pwrmgr
   logic low_power_fall_through;
   logic low_power_abort;
 
-  pwr_flash_t flash_rsp;
+  pwr_nvm_t nvm_rsp;
   pwr_otp_rsp_t otp_rsp;
 
   prim_mubi_pkg::mubi4_t [NumRomInputs-1:0] rom_ctrl_done_async;
@@ -453,9 +453,9 @@ module pwrmgr
     // peripheral signals
     .peri_i(peri_reqs_raw),
 
-    // flash handshake
-    .flash_i(pwr_flash_i),
-    .flash_o(flash_rsp),
+    // NVM handshake
+    .nvm_i(pwr_nvm_i),
+    .nvm_o(nvm_rsp),
 
     // OTP signals
     .otp_i(pwr_otp_i),
@@ -632,8 +632,8 @@ module pwrmgr
     .lc_dft_en_i       (lc_dft_en),
     .lc_hw_debug_en_i  (lc_hw_debug_en),
 
-    // flash
-    .flash_idle_i      (flash_rsp.flash_idle),
+    // NVM
+    .nvm_idle_i        (nvm_rsp.nvm_idle),
 
     // rom_ctrl
     .rom_ctrl_done_i   (rom_ctrl_done_combined),

hw/top_chip/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv

@@ -52,8 +52,8 @@ module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
 
   // peripheral inputs, mixed domains
   input pwr_peri_t peri_i,
-  input pwr_flash_t flash_i,
-  output pwr_flash_t flash_o,
+  input pwr_nvm_t nvm_i,
+  output pwr_nvm_t nvm_o,
 
   // otp interface
   input  pwr_otp_rsp_t otp_i,
@@ -261,11 +261,11 @@ module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
   prim_flop_2sync #(
     .Width(1),
     .ResetValue(1'b1)
-  ) u_sync_flash_idle (
+  ) u_sync_nvm_idle (
     .clk_i,
     .rst_ni,
-    .d_i(flash_i.flash_idle),
-    .q_o(flash_o.flash_idle)
+    .d_i(nvm_i.nvm_idle),
+    .q_o(nvm_o.nvm_idle)
   );
 
   prim_flop_2sync #(

hw/top_chip/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv

@@ -52,8 +52,8 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;(
   input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,
   input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
 
-  // flash
-  input flash_idle_i,
+  // NVM
+  input nvm_idle_i,
 
   // rom_ctrl
   input prim_mubi_pkg::mubi4_t rom_ctrl_done_i,
@@ -398,7 +398,7 @@ module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;(
 
       FastPwrStateNvmIdleChk: begin
 
-        if (otp_idle_i && lc_idle_i && flash_idle_i) begin
+        if (otp_idle_i && lc_idle_i && nvm_idle_i) begin
           state_d = FastPwrStateLowPowerPrep;
         end else begin
           ip_clk_en_d = 1'b1;

hw/top_chip/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv

@@ -115,11 +115,11 @@ package pwrmgr_pkg;
   };
 
   typedef struct packed {
-    logic flash_idle;
-  } pwr_flash_t;
+    logic nvm_idle;
+  } pwr_nvm_t;
 
-  parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
-    flash_idle: 1'b1
+  parameter pwr_nvm_t PWR_NVM_DEFAULT = '{
+    nvm_idle: 1'b1
   };
 
   // cpu reset requests and status

hw/top_chip/rtl/top_chip_system.sv

@@ -749,7 +749,7 @@ module top_chip_system #(
     .pwr_otp_o        ( ),
     .pwr_lc_o         ( ),
     .pwr_lc_i         (lc_ctrl_pkg::PWR_LC_RSP_DEFAULT), // Default to initialised and done.
-    .pwr_flash_i      (pwrmgr_pkg::PWR_FLASH_DEFAULT), // Default to idle.
+    .pwr_nvm_i        (pwrmgr_pkg::PWR_NVM_DEFAULT), // Default to idle.
     .esc_rst_tx_i     (prim_esc_pkg::ESC_RX_DEFAULT),
     .esc_rst_rx_o     ( ),
     .pwr_cpu_i        ('0), // Core is not sleeping.