[vendor, hw, sw] Modify axi_to_mem to support CHERI and integrate it

[thommythomaso]

Addresses #343. Updates #358.

Possible optimizations:

• Parametrize CHERI tag type
• Modify r.user and w.user from logic to a packed struct (see Review AXI crossbar and SRAM tagging #338)
• Non-CHERI-capable managers should not be able to set or check tag bits.

[thommythomaso]

I had to reopen this PR as the visibility change closed #358.
I addressed your feedback: I implemented tag clearing on partial access as well as a separate tag store, and included @raylau1's tests.

[raylau1]

Thanks for the good work! I'm glad to see verilator and FPGA tests passing in CI and dvsim tests passing locally on my side. Note that I'll be on vacation and won't be able to give further reviews next week.

[raylau1]

This will work fine in the current cache-less system but will malfunction with accesses which contain more than 1 capabilities after we integrate caches. I'm not sure if that should be left as a future enhancement. @marnovandermaas what do you think?

[thommythomaso]

I am fully aware of this limitation. How to handle (longer) bursts (of capabilities or mixed data) will be a fundamental question. Currently the burden of detecting valid capability accesses lays with the SRAM controller (which I personally don't find a good idea); adding bursts will make this detection much more complex.

In the presence of a more sophisticated cache, which fetches more than 128 bit at a time, the cache has to ensure to handle sub-capability accesses properly and invalidating them. If this is the case, we can safely remove these checks.