webgpu: Increase MatMulNBits K-parallelism with tile_size_k_vec=32#27834
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webgpu: Increase MatMulNBits K-parallelism with tile_size_k_vec=32#27834
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Pull request overview
Updates the WebGPU MatMulNBits default shader variant to increase K-reduction parallelism on non-Intel GPUs by making tile_size_k_vec configurable and selecting a larger default for better throughput.
Changes:
- Add a
tile_size_k_vecparameter (default16) toMatMulNBitsProgramso K-parallelism can be tuned per device. - Use
tile_size_k_vec = 32for non-Intel adapters and keep16for Intel adapters when constructing the default MatMulNBits program.
Reviewed changes
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| File | Description |
|---|---|
onnxruntime/contrib_ops/webgpu/quantization/matmul_nbits.h |
Extends MatMulNBitsProgram to store a configurable tile_size_k_vec_ used during shader generation. |
onnxruntime/contrib_ops/webgpu/quantization/matmul_nbits.cc |
Plumbs tile_size_k_vec_ into WGSL template parameters and selects 16 vs 32 based on adapter vendor. |
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Use tile_size_k_vec=32 (instead of 16) for MatMulNBits default kernel, doubling the number of threads working on K-dimension reduction per output row. This improves token generation throughput by ~3% on NVIDIA GPUs by better utilizing memory bandwidth. Intel devices retain tile_size_k_vec=16 due to different subgroup and cache characteristics. Changes: - matmul_nbits.h: Add tile_size_k_vec parameter (default 16) to MatMulNBitsProgram constructor. - matmul_nbits.cc: Select tile_size_k_vec=32 for non-Intel vendors, pass to program constructor.
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guschmue
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tile_size_k_vec varies by GPU vendor (32 for NVIDIA, 16 for Intel). Without it in CacheHint, a cached shader compiled with one value could be incorrectly reused when tile_size_k_vec changes, producing wrong results or suboptimal performance.
guschmue
approved these changes
Mar 30, 2026
guschmue
approved these changes
Mar 30, 2026
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Use tile_size_k_vec=32 (instead of 16) for MatMulNBits default kernel, doubling the number of threads working on K-dimension reduction per output row. This improves token generation throughput by ~3% on NVIDIA GPUs by better utilizing memory bandwidth.
Intel devices retain tile_size_k_vec=16 due to different subgroup and cache characteristics.
Changes: