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Merged
mkobetic merged 3 commits into from
Apr 15, 2026
Merged

ARM interrupts #93

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836a2e2
ARM: interrupts
mkobetic Mar 31, 2026
23e0361
prefix constants with ARM_ or RA4_
mkobetic Apr 14, 2026
ed26755
tweaks
mkobetic Apr 15, 2026
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3 changes: 2 additions & 1 deletion arm/amforth.s
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Original file line number Diff line number Diff line change
Expand Up @@ -26,10 +26,11 @@ The default (custom) section flags seem to be CONTENTS and READONLY so not ALLOC
.include "vectors.s"

.section amforth, "ax"
.include "isr.s"

STARTDICT

.include "isr.s"
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@mkobetic mkobetic Apr 13, 2026 •
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I moved this after STARTDICT, because if these files add ARM_CONSTANTS, they will fail if run before STARTDICT.

.include "system.s"
.include "dict_prims.inc"
.include "dict_secs.inc"
.include "dict_env.inc"
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2 changes: 2 additions & 0 deletions arm/isr.s
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@@ -1,3 +1,4 @@
.thumb_func
nullhandler:
push {lr}
push {r1}
Expand All @@ -10,6 +11,7 @@ nullhandler:
pop {r1}
pop {pc}

.thumb_func
faulthandler:
push {lr}
push {r1}
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4 changes: 2 additions & 2 deletions arm/macros.inc
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Expand Up @@ -7,8 +7,8 @@
DEBUG .req r6 @ used when WANT_DEBUGGER == YES
TOS .req r7
DSP .req r8
FW .req r9
FIP .req r10
FW .req r9
FIP .req r10
UP .req r11

@ default register mapping
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3 changes: 2 additions & 1 deletion arm/mcu/ra4m1/amforth.s
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Expand Up @@ -19,10 +19,11 @@
.p2align 2

.section amforth, "ax"
.include "mcu/ra4m1/isr.s"

STARTDICT

.include "isr.s"
.include "system.s"
.include "dict_prims.inc"
.include "dict_secs.inc"
.include "dict_env.inc"
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6 changes: 0 additions & 6 deletions arm/mcu/ra4m1/interrupts.f
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This file was deleted.

21 changes: 1 addition & 20 deletions arm/mcu/ra4m1/isr.s
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@@ -1,22 +1,3 @@
irq_vektor_porta:
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@mkobetic mkobetic Apr 13, 2026

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This was just copied from LM4, and doesn't apply to RA4

irq_vektor_portb:
irq_vektor_portc:
irq_vektor_portd:
irq_vektor_porte:
irq_vektor_portf:
irq_vektor_terminal:

irq_vektor_adc0seq0:
irq_vektor_adc0seq1:
irq_vektor_adc0seq2:
irq_vektor_adc0seq3:

irq_vektor_timer0a:
irq_vektor_timer0b:
irq_vektor_timer1a:
irq_vektor_timer1b:
irq_vektor_timer2a:
irq_vektor_timer2b:

# fall back to nullhandler
.include "arm/isr.s"

175 changes: 43 additions & 132 deletions arm/mcu/ra4m1/vectors.s
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Expand Up @@ -2,136 +2,47 @@
IRQ_VECTORS:
.include "arm/vectors.s"

@ Special interrupt handlers for this particular chip:
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Same here.


.word irq_vektor_porta+1 @ 16: GPIO Port A
.word irq_vektor_portb+1 @ 17: GPIO Port B
.word irq_vektor_portc+1 @ 18: GPIO Port C
.word irq_vektor_portd+1 @ 19: GPIO Port D
.word irq_vektor_porte+1 @ 20: GPIO Port E
.word irq_vektor_terminal+1 @ 21: UART0 Rx and Tx

.word nullhandler+1 @ 22: UART1 Rx and Tx
.word nullhandler+1 @ 23: SSI0 Rx and Tx
.word nullhandler+1 @ 24: I2C0 Master and Slave

.word 0 @ 25: Reserved
.word 0 @ 26: Reserved
.word 0 @ 27: Reserved
.word 0 @ 28: Reserved
.word 0 @ 29: Reserved

.word irq_vektor_adc0seq0+1 @ 30: ADC Sequence 0
.word irq_vektor_adc0seq1+1 @ 31: ADC Sequence 1
.word irq_vektor_adc0seq2+1 @ 32: ADC Sequence 2
.word irq_vektor_adc0seq3+1 @ 33: ADC Sequence 3

.word nullhandler+1 @ 34: Watchdog timers 0 and 1

.word irq_vektor_timer0a+1 @ 35: Timer 0 subtimer A
.word irq_vektor_timer0b+1 @ 36: Timer 0 subtimer B
.word irq_vektor_timer1a+1 @ 37: Timer 1 subtimer A
.word irq_vektor_timer1b+1 @ 38: Timer 1 subtimer B
.word irq_vektor_timer2a+1 @ 39: Timer 2 subtimer A
.word irq_vektor_timer2b+1 @ 40: Timer 2 subtimer B

.word nullhandler+1 @ 41: Analog Comparator 0
.word nullhandler+1 @ 42: Analog Comparator 1

.word 0 @ 43: Reserved

.word nullhandler+1 @ 44: System Control (PLL, OSC, BO)
.word nullhandler+1 @ 45: FLASH Control

.word irq_vektor_portf+1 @ 46: GPIO Port F


.word 0 @ 47: Reserved
.word 0 @ 48: Reserved
.word nullhandler+1 @ 49:
.word nullhandler+1 @ 50:
.word nullhandler+1 @ 51:
.word nullhandler+1 @ 52:
.word nullhandler+1 @ 53:
.word 0 @ 54: Reserved
.word nullhandler+1 @ 55:
.word 0 @ 56: Reserved
.word 0 @ 57: Reserved
.word 0 @ 58: Reserved
.word nullhandler+1 @ 59:
.word nullhandler+1 @ 60:
.word 0 @ 61: Reserved

.word nullhandler+1 @ 62:
.word nullhandler+1 @ 63:
.word nullhandler+1 @ 64:
.word nullhandler+1 @ 65:
.word nullhandler+1 @ 66:
.word nullhandler+1 @ 67:

.word 0 @ 68: Reserved
.word 0 @ 69: Reserved
.word 0 @ 70: Reserved
.word 0 @ 71: Reserved
.word 0 @ 72: Reserved

.word nullhandler+1 @ 73:
.word nullhandler+1 @ 74:
.word nullhandler+1 @ 75:
.word nullhandler+1 @ 76:
.word nullhandler+1 @ 77:
.word nullhandler+1 @ 78:
.word nullhandler+1 @ 79:

.word 0 @ 80: Reserved
.word 0 @ 81: Reserved
.word 0 @ 82: Reserved
.word 0 @ 83: Reserved

.word nullhandler+1 @ 84:
.word nullhandler+1 @ 85:
.word nullhandler+1 @ 86:
.word nullhandler+1 @ 87:

.word 0 @ 88: Reserved
.word 0 @ 89: Reserved
.word 0 @ 90: Reserved
.word 0 @ 91: Reserved
.word 0 @ 92: Reserved
.word 0 @ 93: Reserved
.word 0 @ 94: Reserved
.word 0 @ 95: Reserved
.word 0 @ 96: Reserved
.word 0 @ 97: Reserved
.word 0 @ 98: Reserved
.word 0 @ 99: Reserved
.word 0 @ 100: Reserved
.word 0 @ 101: Reserved
.word 0 @ 102: Reserved
.word 0 @ 103: Reserved
.word 0 @ 104: Reserved
.word 0 @ 105: Reserved
.word 0 @ 106: Reserved
.word 0 @ 107: Reserved

.word nullhandler+1 @ 108:
.word nullhandler+1 @ 109:
.word nullhandler+1 @ 110:
.word nullhandler+1 @ 111:
.word nullhandler+1 @ 112:
.word nullhandler+1 @ 113:
.word nullhandler+1 @ 114:
.word nullhandler+1 @ 115:
.word nullhandler+1 @ 116:
.word nullhandler+1 @ 117:
.word nullhandler+1 @ 118:
.word nullhandler+1 @ 119:
.word nullhandler+1 @ 120:
.word nullhandler+1 @ 121:
.word nullhandler+1 @ 122:

@ 123-154 reserved, space can be used for core instead.

@ move past the vector table space
.org 0x400
/* RA4M1 User Manual
13.3.1 Interrupt Vector Table

13.2.6 ICU Event Link Setting Register n (IELSRn)
Address: 0x40006300 + 4n :
* IELS[7:0] - ICU Event Link Select ; 0 = disabled, otherwise Event Table 13.4.
* IR[16] - Interrupt Status Flag ; write 0 to clear request
* DTCE[24] - DTC Activation Enable ; activates DTC instead of NVIC

*/

.word 0 @ 16: ICU.IELSR0
.word 0 @ 17: ICU.IELSR1
.word 0 @ 18: ICU.IELSR2
.word 0 @ 19: ICU.IELSR3
.word 0 @ 20: ICU.IELSR4
.word 0 @ 21: ICU.IELSR5
.word 0 @ 22: ICU.IELSR6
.word 0 @ 23: ICU.IELSR7
.word 0 @ 24: ICU.IELSR8
.word 0 @ 25: ICU.IELSR9
.word 0 @ 26: ICU.IELSR10
.word 0 @ 27: ICU.IELSR11
.word 0 @ 28: ICU.IELSR12
.word 0 @ 29: ICU.IELSR13
.word 0 @ 30: ICU.IELSR14
.word 0 @ 31: ICU.IELSR15
.word 0 @ 32: ICU.IELSR16
.word 0 @ 33: ICU.IELSR17
.word 0 @ 34: ICU.IELSR18
.word 0 @ 35: ICU.IELSR19
.word 0 @ 36: ICU.IELSR20
.word 0 @ 37: ICU.IELSR21
.word 0 @ 38: ICU.IELSR22
.word 0 @ 39: ICU.IELSR23
.word 0 @ 40: ICU.IELSR24
.word 0 @ 41: ICU.IELSR25
.word 0 @ 42: ICU.IELSR26
.word 0 @ 43: ICU.IELSR27
.word 0 @ 44: ICU.IELSR28
.word 0 @ 45: ICU.IELSR29
.word 0 @ 46: ICU.IELSR30
.word 0 @ 47: ICU.IELSR31

14 changes: 7 additions & 7 deletions arm/mcu/ra4m1/words/at-usart.s
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Expand Up @@ -3,22 +3,22 @@
# using non-FIFO async mode for now.
# TODO: try FIFO
# References:
# * RA4M1 Group: User's Manual (32-bit): 28. Serial Communications Interface (SCI)
# * RA4M1 Group: User Manual (32-bit): 28. Serial Communications Interface (SCI)

# SCI1 Pins
.equ RA4M1_P501PFS, 0x40040940 + 4 * 1 @ TXD1
.equ RA4M1_P502PFS, 0x40040940 + 4 * 2 @ RXD1
.equ RA4_P501PFS, 0x40040940 + 4 * 1 @ TXD1
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@mkobetic mkobetic Apr 14, 2026

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shortening the prefix to just RA4_

.equ RA4_P502PFS, 0x40040940 + 4 * 2 @ RXD1

# UART pins and registers SCI1
.equ AT_UART_BASE, SCI1_BASE
.equ AT_UART_TXD, RA4M1_P501PFS
.equ AT_UART_RXD, RA4M1_P502PFS
.equ AT_UART_STOP, RA4M1_MSTPCRB30
.equ AT_UART_TXD, RA4_P501PFS
.equ AT_UART_RXD, RA4_P502PFS
.equ AT_UART_STOP, RA4_MSTPCRB30

CODEWORD "at-uart-init", AT_UART_INIT

@ Make sure SCI1 module is not stopped
ldr r0, =RA4M1_MSTPCRB
ldr r0, =RA4_MSTPCRB
ldr r1, [r0]
bic r1, r1, #AT_UART_STOP
str r1, [r0]
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10 changes: 5 additions & 5 deletions arm/mcu/ra4m1/words/clock.s
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@@ -1,5 +1,5 @@
# System Clock Support
# RA4M1 Group: User's Manual (32-bit): 8. Clock Generation Circuit
# RA4M1 Group: User Manual (32-bit): 8. Clock Generation Circuit
# Table 8.1 Clock sources:
# * Main clock oscillator (MOSC): 1-20MHz (2.4V < VCC <= 5.5V => 1 - 20 MHz)
# * Sub-clock oscillator (SOSC): 32768Hz
Expand All @@ -15,12 +15,12 @@
# * PCLKB, FCLK = 24 MHz

# Option Setting Memory Registers (6. Option Setting Memory)
.equ RA4M1_OFS0, 0x00000400 @ Option Function Select Register 0 (32-bit) I/WDT
.equ RA4M1_OFS1, 0x00000404 @ Option Function Select Register 1 (32-bit) HOCO & voltage detection
.equ RA4_OFS0, 0x00000400 @ Option Function Select Register 0 (32-bit) I/WDT
.equ RA4_OFS1, 0x00000404 @ Option Function Select Register 1 (32-bit) HOCO & voltage detection
# [08] HOCOEN = HOCO Oscillation Enable ; UNOR4 = 1 => enabled
# [14:12] HOCOFRQ = 24MHz(0), 32MHz(2), 48Mhz(4), 64Mhz(5) ; UNOR4 = 4 => 48MHz

.equ RA4M1_SCKDIVCR , 0x4001E020 @ System Clock Division Control Register (32-bit)
.equ RA4_SCKDIVCR , 0x4001E020 @ System Clock Division Control Register (32-bit)
# for each clock below n = 0..6 => 1/2^n, i.e 1/1 ... 1/64
# reset => 4 i.e. 1/16 division
# [30:28] FCLK (Flash interface clock) UNOR4 = 1
Expand All @@ -31,7 +31,7 @@
# [06:04] PCLKC (ADC14 conversion clock) UNOR4 = 0
# [02:00] PCLKD (GPT count clock) UNOR4 = 0

.equ RA4M1_SCKSCR, 0x4001E026 @ System Clock Source Control Register (8-bit)
.equ RA4_SCKSCR, 0x4001E026 @ System Clock Source Control Register (8-bit)
# [02:00] CKSEL = HOCO(0), MOCO(1), LOCO(2), MOSC(3), SOSC(4), PLL(5) ; UNOR4 = 0 => HOCO
# reset => MOCO

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