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Enable iface clock for kodiak and monaco ice sdhc#908

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kuld-sing wants to merge 2 commits intoqualcomm-linux:tech/security/icefrom
kuld-sing:tech/security/ice
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Enable iface clock for kodiak and monaco ice sdhc#908
kuld-sing wants to merge 2 commits intoqualcomm-linux:tech/security/icefrom
kuld-sing:tech/security/ice

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As ice is now standalone driver decoupled from ufs driver.
MMC ice controller should also now specify iface clock alongwith core
clock.

The patchset is motivation to fix ice mmc where ice ufs is fixed with
below series.
https://lore.kernel.org/linux-arm-msm/20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com/T/#m5da5dd7a18318583b23ffeb42fa07ef1438042d5

Testing:

  • dtbs check
  • Custom monaco/kodiak device with emmc storage.

Kuldeep Singh added 2 commits April 8, 2026 00:08
Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core'
clock the 'iface' clock should also be turned on by the driver.

As bindings allow to specify 2 clocks, add iface clock now.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/linux-arm-msm/20260406-ice_emmc_clock_addition-v1-1-e7b237bf7a69@oss.qualcomm.com/
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core'
clock the 'iface' clock should also be turned on by the driver.

As bindings allow to specify 2 clocks, add iface clock now.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/linux-arm-msm/20260406-ice_emmc_clock_addition-v1-2-e7b237bf7a69@oss.qualcomm.com/
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
@kuld-sing kuld-sing force-pushed the tech/security/ice branch from 510df6f to 61b2782 Compare April 7, 2026 18:39
reg = <0x0 0x007c8000 0x0 0x18000>;
clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
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@arakshit011 arakshit011 Apr 7, 2026

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Does this not need power domain?

reg = <0x0 0x087c8000 0x0 0x18000>;
clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
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Same here.

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2 participants