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Kaanapali gpu mainline #910

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f92d664
PENDING: arm64: dts: qcom: kaanapali: add the GPU SMMU node
quic-qqzhou Jul 17, 2025
b36589d
PENDING: arm64: dts: qcom: Add GPU support for Kaanapali
akhilpo-qcom Aug 26, 2025
3b20bfe
PENDING: arm64: dts: qcom: kaanapali-qrd: Enable GPU
akhilpo-qcom Sep 20, 2025
ed5ec15
PENDING: arm64: dts: qcom: kaanapali-mtp: Enable GPU
akhilpo-qcom Sep 20, 2025
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8 changes: 8 additions & 0 deletions arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -870,6 +870,14 @@
};
};

&gpu {
status = "okay";
};

&gpu_zap_shader {
firmware-name = "qcom/kaanapali/gen80200_zap.mbn";
};

&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
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8 changes: 8 additions & 0 deletions arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -698,6 +698,14 @@
};
};

&gpu {
status = "okay";
};

&gpu_zap_shader {
firmware-name = "qcom/kaanapali/gen80200_zap.mbn";
};

&pmh0101_flash {
status = "okay";

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241 changes: 241 additions & 0 deletions arch/arm64/boot/dts/qcom/kaanapali.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2715,6 +2715,204 @@
#power-domain-cells = <1>;
};

gpu: gpu@3d00000 {
compatible = "qcom,adreno-44050a01", "qcom,adreno";
reg = <0x0 0x03d00000 0x0 0x40000>,
<0x0 0x03d9e000 0x0 0x2000>,
<0x0 0x03d61000 0x0 0x800>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem",
"cx_dbgc";

interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

iommus = <&adreno_smmu 0 0x0>,
<&adreno_smmu 1 0x0>;

operating-points-v2 = <&gpu_opp_table>;

qcom,gmu = <&gmu>;
#cooling-cells = <2>;

interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";

gpu_zap_shader: zap-shader {
memory-region = <&gpu_microcode_mem>;
};

gpu_opp_table: opp-table {
compatible = "operating-points-v2-adreno",
"operating-points-v2";

opp-222000000 {
opp-hz = /bits/ 64 <222000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
opp-peak-kBps = <2136718>;
};

opp-282000000 {
opp-hz = /bits/ 64 <282000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>;
opp-peak-kBps = <5285156>;
qcom,opp-acd-level = <0xca2e5ffd>;
};

opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <5285156>;
qcom,opp-acd-level = <0xe22a5ffd>;
};

opp-382000000 {
opp-hz = /bits/ 64 <382000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
opp-peak-kBps = <5285156>;
qcom,opp-acd-level = <0xa22c5ffd>;
};

opp-422000000 {
opp-hz = /bits/ 64 <422000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <6074218>;
qcom,opp-acd-level = <0xa22c5ffd>;
};

opp-461000000 {
opp-hz = /bits/ 64 <461000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>;
opp-peak-kBps = <6074218>;
qcom,opp-acd-level = <0xe82e5ffd>;
};

opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
opp-peak-kBps = <6074218>;
qcom,opp-acd-level = <0xe82c5ffd>;
};

opp-539000000 {
opp-hz = /bits/ 64 <539000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
opp-peak-kBps = <6074218>;
qcom,opp-acd-level = <0xc82b5ffd>;
};

opp-578000000 {
opp-hz = /bits/ 64 <578000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074218>;
qcom,opp-acd-level = <0xc02c5ffd>;
};

opp-646000000 {
opp-hz = /bits/ 64 <646000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
opp-peak-kBps = <8171875>;
qcom,opp-acd-level = <0xc02c5ffd>;
};

opp-726000000 {
opp-hz = /bits/ 64 <726000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <8171875>;
qcom,opp-acd-level = <0x882f5ffd>;
};

opp-826000000 {
opp-hz = /bits/ 64 <826000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <12449218>;
qcom,opp-acd-level = <0xa82c5ffd>;
};

opp-902000000 {
opp-hz = /bits/ 64 <902000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449218>;
qcom,opp-acd-level = <0xa82b5ffd>;
};

opp-967000000 {
opp-hz = /bits/ 64 <967000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <12449218>;
qcom,opp-acd-level = <0x882a5ffd>;
};

opp-105000000 {
opp-hz = /bits/ 64 <105000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <20832031>;
qcom,opp-acd-level = <0x88295ffd>;
};
};
};

gmu: gmu@3d6a000 {
compatible = "qcom,adreno-gmu-840.1", "qcom,adreno-gmu";

reg = <0x0 0x03d37000 0x0 0x68000>;
reg-names = "gmu";

interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";

clocks = <&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "ahb",
"gmu",
"cxo",
"memnoc",
"hub";

power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gxclkctl GX_CLKCTL_GX_GDSC>;
power-domain-names = "cx",
"gx";

iommus = <&adreno_smmu 5 0x0>;

qcom,qmp = <&aoss_qmp>;
operating-points-v2 = <&gmu_opp_table>;

gmu_opp_table: opp-table {
compatible = "operating-points-v2";

opp-475000000 {
opp-hz = /bits/ 64 <475000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
};

opp-575000000 {
opp-hz = /bits/ 64 <575000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};

opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};

opp-725000000 {
opp-hz = /bits/ 64 <725000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};

opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
};
};

gxclkctl: clock-controller@3d64000 {
compatible = "qcom,kaanapali-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
Expand All @@ -2739,6 +2937,49 @@
#power-domain-cells = <1>;
};

adreno_smmu: iommu@3da0000 {
compatible = "qcom,kaanapali-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x3da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;

power-domains = <&gpucc GPU_CC_CX_GDSC>;
interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "gpu_cc_gpu_smmu_vote_clk";

interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
};

remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
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