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WORKAROUND: Enable ethernet on Talos Ride SX #267

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WORKAROUND: Enable ethernet on Talos Ride SX #267

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9c47fe9
FROMLIST: net: stmmac: Inverse the phy-mode definition
yijiyang Feb 11, 2026
773ee6e
FROMLIST: arm64: dts: qcom: talos: add ethernet node
yijiyang Feb 11, 2026
361fefe
FROMLIST: arm64: dts: qcom: qcs615-ride: Enable ethernet node
yijiyang Feb 11, 2026
74fe063
WORKAROUND: net: stmmac: qcom-ethqos: Enable RX_PROG_SWAP for all tar…
ayaan-anwar Feb 11, 2026
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102 changes: 102 additions & 0 deletions arch/arm64/boot/dts/qcom/qcs615-ride.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -372,6 +372,59 @@
};
};

&ethernet {
pinctrl-0 = <&ethernet_defaults>;
pinctrl-names = "default";

phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-id";

snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;

status = "okay";

mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;

rgmii_phy: phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x7>;

interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
device_type = "ethernet-phy";
reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};

mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
snps,rx-sched-sp;

queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
};

mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
snps,tx-sched-wrr;

queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x0>;
};
};
};

&gpu {
status = "okay";
};
Expand Down Expand Up @@ -552,6 +605,55 @@
};

&tlmm {
ethernet_defaults: ethernet-defaults-state {
mdc-pins {
pins = "gpio113";
function = "rgmii";
bias-pull-up;
};

mdio-pins {
pins = "gpio114";
function = "rgmii";
bias-pull-up;
};

rgmii-rx-pins {
pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112";
function = "rgmii";
bias-disable;
drive-strength = <2>;
};

rgmii-tx-pins {
pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97";
function = "rgmii";
bias-pull-up;
drive-strength = <16>;
};

phy-intr-pins {
pins = "gpio121";
function = "gpio";
bias-disable;
drive-strength = <8>;
};

pps-pins {
pins = "gpio91";
function = "rgmii";
bias-disable;
drive-strength = <8>;
};

phy-reset-pins {
pins = "gpio104";
function = "gpio";
bias-pull-up;
drive-strength = <16>;
};
};

bt_en_state: bt-en-state {
pins = "gpio85";
function = "gpio";
Expand Down
34 changes: 34 additions & 0 deletions arch/arm64/boot/dts/qcom/talos.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -678,6 +678,40 @@
#address-cells = <2>;
#size-cells = <2>;

ethernet: ethernet@20000 {
compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos";
reg = <0x0 0x00020000 0x0 0x10000>,
<0x0 0x00036000 0x0 0x100>;
reg-names = "stmmaceth",
"rgmii";

clocks = <&gcc GCC_EMAC_AXI_CLK>,
<&gcc GCC_EMAC_SLV_AHB_CLK>,
<&gcc GCC_EMAC_PTP_CLK>,
<&gcc GCC_EMAC_RGMII_CLK>;
clock-names = "stmmaceth",
"pclk",
"ptp_ref",
"rgmii";

interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq",
"eth_lpi";

power-domains = <&gcc EMAC_GDSC>;
resets = <&gcc GCC_EMAC_BCR>;

iommus = <&apps_smmu 0x1c0 0x0>;

snps,tso;
snps,pbl = <32>;
rx-fifo-depth = <16384>;
tx-fifo-depth = <20480>;

status = "disabled";
};

gcc: clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0 0x00100000 0 0x1f0000>;
Expand Down
35 changes: 16 additions & 19 deletions drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
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Original file line number Diff line number Diff line change
Expand Up @@ -387,14 +387,11 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
{
struct device *dev = &ethqos->pdev->dev;
int phase_shift;
int phase_shift = 0;
int loopback;

/* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
phase_shift = 0;
else
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;

/* Disable loopback mode */
Expand Down Expand Up @@ -471,13 +468,9 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0, RGMII_IO_MACRO_CONFIG2);

if (ethqos->has_emac_ge_3)
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);
else
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
0, RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);

/* Write 0x5 to PRG_RCLK_DLY_CODE */
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
Expand Down Expand Up @@ -511,13 +504,10 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
RGMII_IO_MACRO_CONFIG);
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
0, RGMII_IO_MACRO_CONFIG2);
if (ethqos->has_emac_ge_3)
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);
else
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
0, RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_CONFIG2_RX_PROG_SWAP,
RGMII_IO_MACRO_CONFIG2);

/* Write 0x5 to PRG_RCLK_DLY_CODE */
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
Expand Down Expand Up @@ -789,7 +779,14 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
if (!ethqos)
return -ENOMEM;

/* Qualcomm configures the MAC to introduce delay; instruct the
* PHY not to add additional delay.
*/
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RGMII_ID)
plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;

ethqos->phy_mode = plat_dat->phy_interface;

switch (ethqos->phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
Expand Down