Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
This repository documents my journey in the RISC-V Reference SoC Tapeout Program. The first 10 weeks focus on RTL design, synthesis, simulation, and verification using open-source tools like Yosys, Icarus Verilog, GTKWave, and OpenLane, building a foundation for full-chip tapeout.
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.
RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.
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