Pinned Loading

1. Satellite-Data-Telemetry-with-an-ESP32 Satellite-Data-Telemetry-with-an-ESP32 Public

   Simulating Hardware in a Loop, Running a TFLite model on ESP32 as an arduno .h header file and adding the model as a library from the .ZIP file option

   C 1

2. RISC RISC Public

   Single Cycle Processor based on RISC -V Architecture

   Verilog

3. BCD_Adder BCD_Adder Public

   Verilog implementation of a BCD adder along with it's test bench

   Verilog

4. Find_Patterns Find_Patterns Public

   This project implements a Finite State Machine (FSM) in Verilog to detect the sequence "11" in a serial stream of binary inputs. The FSM is designed as a Mealy machine: the output depends on both t…

   Verilog

5. semaphore_challenge semaphore_challenge Public

   Using semaphores and mutexes protect a buffer of size 5 from 5 producer tasks printing their task number three times each and 2 consumer task freeing up 1 buffer space at a time

   C++

6. Hexdump Hexdump Public

   hexdump utility written in c, to run : 1) make ,2) ./hexdump sample.txt

   C 1