[ET-VK][conv1d] Implement height-packed depthwise conv1d operator

[SS-JIA]

Stack from ghstack (oldest at bottom):

• [ET-VK][CI] Add test-vulkan-genai job for Parakeet on NVIDIA GPU runner #18335
• [ET-VK][conv1d] Route conv1d to height-packed implementations in export pipeline #18334
• -> [ET-VK][conv1d] Implement height-packed depthwise conv1d operator #18333
• [ET-VK][conv1d] Implement height-packed pointwise conv1d operator #18332

Implement a depthwise conv1d operator using height-packed layout where channels
are the packed dimension (WHCN dim 1). Depthwise conv applies a separate filter
to each channel independently (groups=C), so 4 channels can be processed in
parallel using element-wise vec4 FMA over kernel positions.

Thread mapping: X=C/4, Y=L_out, Z=N. Each thread computes one output texel
(4 channels at one spatial position). Inner loop iterates over kernel positions
K with bounds-checked input access for padding.

Weight [C,1,K] is prepacked as channels-packed so each vec4 load gives 4
channels' weights at one kernel position. Supports both buffer and texture3d
storage, fp32/fp16, optional bias, and arbitrary stride/padding/dilation.
Registered as et_vk.conv1d_dw.default (standalone custom op).

Performance on Adreno 750 (S24):

• [1,128,4096] K=31 buffer f16: 231 GFLOP/s
• [1,128,4096] K=31 buffer f32: 155 GFLOP/s
• [1,512,2048] K=5 buffer f32: 66 GFLOP/s

Differential Revision: D97344091

[pytorch-bot]

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🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/18333

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✅ You can merge normally! (2 Unrelated Failures)

As of commit 2d4d76c with merge base 9076110 ():

FLAKY - The following jobs failed but were likely due to flakiness present on trunk:

• pull / unittest / windows / windows-job (gh) (matched win rule in flaky-rules.json)
  ##[error]The operation was canceled.
• pull / unittest-editable / windows / windows-job (gh) (matched win rule in flaky-rules.json)
  ##[error]The operation was canceled.

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